397 lines
21 KiB
C
397 lines
21 KiB
C
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/* ###################################################################
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** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
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** Filename : USB0.c
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** Project : Landungsbruecke_KDS_v2.0.0
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** Processor : MK20DN512VLL10
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** Component : Init_USB_OTG
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** Version : Component 01.004, Driver 01.04, CPU db: 3.00.000
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** Compiler : GNU C Compiler
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** Date/Time : 2015-01-09, 16:27, # CodeGen: 0
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** Abstract :
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** This file implements the USB_OTG (USB0) module initialization
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** according to the Peripheral Initialization settings, and
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** defines interrupt service routines prototypes.
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** Settings :
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** Component name : USB0
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** Device : USB0
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** Settings :
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** Clock gate : Enabled
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** Clock settings :
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** Clock divider :
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** Clock divider source : PLL/FLL clock
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** Clock divider input frequency : 96 MHz
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** Clock divider fraction : multiply by 1
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** Clock divider divisor : divide by 2
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** Module clock source : Clock divider output
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** Module clock frequency : 48 MHz
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** Pull-up/pull-down settings :
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** Weak pulldowns : Enabled
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** Pull-up/pull-down control : Mode dependent
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** D+ pull-up : Disabled
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** D+ pull-down : Disabled
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** D- pull-down : Disabled
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** D+ pull-up for non-OTG mode : Disabled
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** Endpoints :
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** EP0 : Disabled
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** Direct low speed : Disabled
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** Retry : Enabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP1 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP2 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP3 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP4 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP5 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP6 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP7 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP8 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP9 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP10 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP11 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP12 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP13 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP14 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** EP15 : Disabled
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** Setup transfers : Enabled
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** Handshake : Disabled
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** Rx transfer : Disabled
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** Tx transfer : Disabled
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** Force stall : Disabled
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** Buffer descriptor table :
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** External object declaration : extern uint8 g_Mem[];
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** Address : ((uint32)&g_Mem[0])
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** SOF threshold : 0
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** Pins :
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** Alternate clock source : Disabled
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** SOF output : Disabled
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** Data plus : Enabled
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** Pin : USB0_DP
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** Pin signal :
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** Data minus : Enabled
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** Pin : USB0_DM
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** Pin signal :
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** Interrupts :
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** USB :
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** Interrupt : INT_USB0
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** Interrupt request : Disabled
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** Interrupt priority : 0 (Highest)
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** ISR Name : USB_ISR
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** Stall : Enabled
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** Attach : Enabled
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** Resume : Enabled
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** Sleep : Enabled
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** Token OK : Enabled
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** Start of frame : Enabled
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** Error interrupt : Enabled
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** USB reset : Enabled
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** Asynchronous Resume interrupt : Enabled
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** Error interrupts :
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** Bit stuff error : Disabled
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** DMA error : Disabled
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** Bus turnaround timeout : Disabled
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** Data length error : Disabled
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** CRC16 error : Disabled
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** CRC5 or EOF : Disabled
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** PID error : Disabled
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** OTG interrupts :
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** ID pin changed : Disabled
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** 1 ms interrupt : Disabled
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** Line stage change : Disabled
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** Session valid : Disabled
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** "B" session end : Disabled
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** "A" bus valid : Disabled
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** Initialization :
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** Mode : Device
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** USB transceiver suspend state : Enabled
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** Call Init method : yes
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** Contents :
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** Init - void USB0_Init(void);
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**
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** Copyright : 1997 - 2014 Freescale Semiconductor, Inc.
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** All Rights Reserved.
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**
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** o Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** o Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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** ###################################################################*/
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/*!
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** @file USB0.c
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** @version 01.04
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** @brief
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** This file implements the USB_OTG (USB0) module initialization
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** according to the Peripheral Initialization settings, and
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** defines interrupt service routines prototypes.
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*/
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/*!
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** @addtogroup USB0_module USB0 module documentation
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** @{
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*/
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/* MODULE USB0. */
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#include "USB0.h"
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/* Including shared modules, which are used in the whole project */
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#include "PE_Types.h"
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#include "PE_Error.h"
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#include "PE_Const.h"
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#include "hal/derivative.h"
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/*
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** ===================================================================
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** Method : USB0_Init (component Init_USB_OTG)
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** Description :
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** This method initializes registers of the USB_OTG module
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** according to the Peripheral Initialization settings.
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** Call this method in user code to initialize the module. By
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** default, the method is called by PE automatically; see "Call
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** Init method" property of the component for more details.
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** Parameters : None
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** Returns : Nothing
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** ===================================================================
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*/
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extern uint8 g_Mem[];
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void USB0_Init(void)
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{
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/* SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */
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SIM_CLKDIV2 = (uint32)((SIM_CLKDIV2 & (uint32)~(uint32)(
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SIM_CLKDIV2_USBDIV(0x06) |
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SIM_CLKDIV2_USBFRAC_MASK
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)) | (uint32)(
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SIM_CLKDIV2_USBDIV(0x01)
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));
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/* SIM_SOPT2: USBSRC=1 */
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SIM_SOPT2 |= SIM_SOPT2_USBSRC_MASK;
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/* SIM_SCGC4: USBOTG=1 */
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SIM_SCGC4 |= SIM_SCGC4_USBOTG_MASK;
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/* USB0_CTL: ODDRST=1 */
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USB0_CTL |= USB_CTL_ODDRST_MASK;
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/* USB0_USBCTRL: SUSP=1,PDE=1,??=0,??=0,??=0,??=0,??=0,??=0 */
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USB0_USBCTRL = (USB_USBCTRL_SUSP_MASK | USB_USBCTRL_PDE_MASK);
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/* USB0_OTGISTAT: IDCHG=1,ONEMSEC=1,LINE_STATE_CHG=1,??=1,SESSVLDCHG=1,B_SESS_CHG=1,??=1,AVBUSCHG=1 */
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USB0_OTGISTAT = USB_OTGISTAT_IDCHG_MASK |
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USB_OTGISTAT_ONEMSEC_MASK |
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USB_OTGISTAT_LINE_STATE_CHG_MASK |
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USB_OTGISTAT_SESSVLDCHG_MASK |
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USB_OTGISTAT_B_SESS_CHG_MASK |
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USB_OTGISTAT_AVBUSCHG_MASK |
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0x12U;
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/* USB0_ISTAT: STALL=1,ATTACH=1,RESUME=1,SLEEP=1,TOKDNE=1,SOFTOK=1,ERROR=1,USBRST=1 */
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USB0_ISTAT = USB_ISTAT_STALL_MASK |
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USB_ISTAT_ATTACH_MASK |
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USB_ISTAT_RESUME_MASK |
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USB_ISTAT_SLEEP_MASK |
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USB_ISTAT_TOKDNE_MASK |
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USB_ISTAT_SOFTOK_MASK |
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USB_ISTAT_ERROR_MASK |
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USB_ISTAT_USBRST_MASK;
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/* USB0_ERRSTAT: BTSERR=1,??=1,DMAERR=1,BTOERR=1,DFN8=1,CRC16=1,CRC5EOF=1,PIDERR=1 */
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USB0_ERRSTAT = USB_ERRSTAT_BTSERR_MASK |
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USB_ERRSTAT_DMAERR_MASK |
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USB_ERRSTAT_BTOERR_MASK |
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USB_ERRSTAT_DFN8_MASK |
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USB_ERRSTAT_CRC16_MASK |
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USB_ERRSTAT_CRC5EOF_MASK |
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USB_ERRSTAT_PIDERR_MASK |
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0x40U;
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/* USB0_INTEN: STALLEN=1,ATTACHEN=1,RESUMEEN=1,SLEEPEN=1,TOKDNEEN=1,SOFTOKEN=1,ERROREN=1,USBRSTEN=1 */
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USB0_INTEN = USB_INTEN_STALLEN_MASK |
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USB_INTEN_ATTACHEN_MASK |
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USB_INTEN_RESUMEEN_MASK |
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USB_INTEN_SLEEPEN_MASK |
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USB_INTEN_TOKDNEEN_MASK |
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USB_INTEN_SOFTOKEN_MASK |
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USB_INTEN_ERROREN_MASK |
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USB_INTEN_USBRSTEN_MASK;
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/* USB0_ERREN: BTSERREN=0,??=0,DMAERREN=0,BTOERREN=0,DFN8EN=0,CRC16EN=0,CRC5EOFEN=0,PIDERREN=0 */
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USB0_ERREN = 0x00U;
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/* USB0_USBTRC0: USBRESET=0,??=1,USBRESMEN=1,??=0,??=0,??=0,SYNC_DET=0,USB_RESUME_INT=0 */
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USB0_USBTRC0 = (USB_USBTRC0_USBRESMEN_MASK | 0x40U);
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/* USB0_OTGICR: IDEN=0,ONEMSECEN=0,LINESTATEEN=0,??=0,SESSVLDEN=0,BSESSEN=0,??=0,AVBUSEN=0 */
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USB0_OTGICR = 0x00U;
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/* USB0_ADDR: LSEN=0,ADDR=0 */
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USB0_ADDR = USB_ADDR_ADDR(0x00);
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/* USB0_ENDPT0: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT0 = 0x00U;
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/* USB0_ENDPT1: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT1 = 0x00U;
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/* USB0_ENDPT2: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT2 = 0x00U;
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/* USB0_ENDPT3: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT3 = 0x00U;
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/* USB0_ENDPT4: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT4 = 0x00U;
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/* USB0_ENDPT5: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT5 = 0x00U;
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/* USB0_ENDPT6: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT6 = 0x00U;
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/* USB0_ENDPT7: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT7 = 0x00U;
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/* USB0_ENDPT8: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
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USB0_ENDPT8 = 0x00U;
|
||
|
|
/* USB0_ENDPT9: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
|
||
|
|
USB0_ENDPT9 = 0x00U;
|
||
|
|
/* USB0_ENDPT10: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
|
||
|
|
USB0_ENDPT10 = 0x00U;
|
||
|
|
/* USB0_ENDPT11: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
|
||
|
|
USB0_ENDPT11 = 0x00U;
|
||
|
|
/* USB0_ENDPT12: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
|
||
|
|
USB0_ENDPT12 = 0x00U;
|
||
|
|
/* USB0_ENDPT13: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
|
||
|
|
USB0_ENDPT13 = 0x00U;
|
||
|
|
/* USB0_ENDPT14: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
|
||
|
|
USB0_ENDPT14 = 0x00U;
|
||
|
|
/* USB0_ENDPT15: HOSTWOHUB=0,RETRYDIS=0,??=0,EPCTLDIS=0,EPRXEN=0,EPTXEN=0,EPSTALL=0,EPHSHK=0 */
|
||
|
|
USB0_ENDPT15 = 0x00U;
|
||
|
|
USB0_BDTPAGE1 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x08) & 0xFEU);
|
||
|
|
USB0_BDTPAGE2 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x10) & 0xFFU);
|
||
|
|
USB0_BDTPAGE3 = (uint8)((((uint32)((uint32)&g_Mem[0])) >> 0x18) & 0xFFU);
|
||
|
|
/* USB0_SOFTHLD: CNT=0 */
|
||
|
|
USB0_SOFTHLD = USB_SOFTHLD_CNT(0x00);
|
||
|
|
/* USB0_OTGCTL: DPHIGH=0,??=0,DPLOW=0,DMLOW=0,??=0,OTGEN=0,??=0,??=0 */
|
||
|
|
USB0_OTGCTL = 0x00U;
|
||
|
|
/* USB0_CONTROL: ??=0,??=0,??=0,DPPULLUPNONOTG=0,??=0,??=0,??=0,??=0 */
|
||
|
|
USB0_CONTROL = 0x00U;
|
||
|
|
/* USB0_CTL: TXSUSPENDTOKENBUSY=0,HOSTMODEEN=0,ODDRST=0,USBENSOFEN=1 */
|
||
|
|
USB0_CTL = (uint8)((USB0_CTL & (uint8)~(uint8)(
|
||
|
|
USB_CTL_TXSUSPENDTOKENBUSY_MASK |
|
||
|
|
USB_CTL_HOSTMODEEN_MASK |
|
||
|
|
USB_CTL_ODDRST_MASK
|
||
|
|
)) | (uint8)(
|
||
|
|
USB_CTL_USBENSOFEN_MASK
|
||
|
|
));
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
** ###################################################################
|
||
|
|
**
|
||
|
|
** The interrupt service routine(s) must be implemented
|
||
|
|
** by user in one of the following user modules.
|
||
|
|
**
|
||
|
|
** If the "Generate ISR" option is enabled, Processor Expert generates
|
||
|
|
** ISR templates in the CPU event module.
|
||
|
|
**
|
||
|
|
** User modules:
|
||
|
|
** main.c
|
||
|
|
** Events.c
|
||
|
|
**
|
||
|
|
** ###################################################################
|
||
|
|
PE_ISR(USB_ISR)
|
||
|
|
{
|
||
|
|
// NOTE: The routine should include actions to clear the appropriate
|
||
|
|
// interrupt flags.
|
||
|
|
//
|
||
|
|
}
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/* END USB0. */
|
||
|
|
/*!
|
||
|
|
** @}
|
||
|
|
*/
|
||
|
|
/*
|
||
|
|
** ###################################################################
|
||
|
|
**
|
||
|
|
** This file was created by Processor Expert 10.4 [05.11]
|
||
|
|
** for the Freescale Kinetis series of microcontrollers.
|
||
|
|
**
|
||
|
|
** ###################################################################
|
||
|
|
*/
|