//#include "typedefs.h" /* ** ################################################################### ** Processors: MK20DN512VLK10 ** MK20DX256VLK10 ** MK20DN512VLL10 ** MK20DX256VLL10 ** MK20DN512VLQ10 ** MK20DX128VLQ10 ** MK20DX256VLQ10 ** MK20DN512VMB10 ** MK20DX256VMB10 ** MK20DN512VMC10 ** MK20DX256VMC10 ** MK20DN512VMD10 ** MK20DX256VMD10 ** MK20DX128VMD10 ** ** Compilers: ARM Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: K20P144M100SF2V2RM Rev. 1, Jan 2012 ** Version: rev. 1.1, 2012-01-10 ** ** Abstract: ** This header file implements peripheral memory map for MK20D10 ** processor. ** ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 1.0 (2011-09-15) ** Initial version ** - rev. 1.1 (2012-01-10) ** Registers updated according to the new reference manual revision - Rev. 1, Jan 2012 ** ** ################################################################### */ /** * @file MK20D10.h * @version 1.1 * @date 2012-01-10 * @brief Peripheral memory map for MK20D10 * * This header file implements peripheral memory map for MK20D10 processor. */ /* ---------------------------------------------------------------------------- -- MCU activation ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ #if !defined(MCU_MK20D10) /* Check if memory map has not been already included */ #define MCU_MK20D10 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) #error MK20D10 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE #include /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100u /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0001u /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG(Reg,Bit) (*((uint32 volatile*)(0x42000000u + (32u*((uint32)&(Reg) - (uint32)0x40000000u)) + (4u*((uint32)(Bit)))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /** * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ typedef enum { INT_Initial_Stack_Pointer = 0, /**< Initial Stack Pointer */ INT_Initial_Program_Counter = 1, /**< Initial Program Counter */ INT_NMI = 2, /**< Non-maskable Interrupt (NMI) */ INT_Hard_Fault = 3, /**< Hard Fault */ INT_Mem_Manage_Fault = 4, /**< MemManage Fault */ INT_Bus_Fault = 5, /**< Bus Fault */ INT_Usage_Fault = 6, /**< Usage Fault */ INT_Reserved7 = 7, /**< Reserved interrupt 7 */ INT_Reserved8 = 8, /**< Reserved interrupt 8 */ INT_Reserved9 = 9, /**< Reserved interrupt 9 */ INT_Reserved10 = 10, /**< Reserved interrupt 10 */ INT_SVCall = 11, /**< Supervisor call (SVCall) */ INT_DebugMonitor = 12, /**< Debug Monitor */ INT_Reserved13 = 13, /**< Reserved interrupt 13 */ INT_PendableSrvReq = 14, /**< Pendable request for system service (PendableSrvReq) */ INT_SysTick = 15, /**< SysTick Interrupt */ INT_DMA0 = 16, /**< DMA Channel 0 Transfer Complete */ INT_DMA1 = 17, /**< DMA Channel 1 Transfer Complete */ INT_DMA2 = 18, /**< DMA Channel 2 Transfer Complete */ INT_DMA3 = 19, /**< DMA Channel 3 Transfer Complete */ INT_DMA4 = 20, /**< DMA Channel 4 Transfer Complete */ INT_DMA5 = 21, /**< DMA Channel 5 Transfer Complete */ INT_DMA6 = 22, /**< DMA Channel 6 Transfer Complete */ INT_DMA7 = 23, /**< DMA Channel 7 Transfer Complete */ INT_DMA8 = 24, /**< DMA Channel 8 Transfer Complete */ INT_DMA9 = 25, /**< DMA Channel 9 Transfer Complete */ INT_DMA10 = 26, /**< DMA Channel 10 Transfer Complete */ INT_DMA11 = 27, /**< DMA Channel 11 Transfer Complete */ INT_DMA12 = 28, /**< DMA Channel 12 Transfer Complete */ INT_DMA13 = 29, /**< DMA Channel 13 Transfer Complete */ INT_DMA14 = 30, /**< DMA Channel 14 Transfer Complete */ INT_DMA15 = 31, /**< DMA Channel 15 Transfer Complete */ INT_DMA_Error = 32, /**< DMA Error Interrupt */ INT_MCM = 33, /**< Normal Interrupt */ INT_FTFL = 34, /**< FTFL Interrupt */ INT_Read_Collision = 35, /**< Read Collision Interrupt */ INT_LVD_LVW = 36, /**< Low Voltage Detect, Low Voltage Warning */ INT_LLW = 37, /**< Low Leakage Wakeup */ INT_Watchdog = 38, /**< WDOG Interrupt */ INT_Reserved39 = 39, /**< Reserved Interrupt 39 */ INT_I2C0 = 40, /**< I2C0 interrupt */ INT_I2C1 = 41, /**< I2C1 interrupt */ INT_SPI0 = 42, /**< SPI0 Interrupt */ INT_SPI1 = 43, /**< SPI1 Interrupt */ INT_SPI2 = 44, /**< SPI2 Interrupt */ INT_CAN0_ORed_Message_buffer = 45, /**< CAN0 OR'd message buffers interrupt */ INT_CAN0_Bus_Off = 46, /**< CAN0 bus off interrupt */ INT_CAN0_Error = 47, /**< CAN0 error interrupt */ INT_CAN0_Tx_Warning = 48, /**< CAN0 Tx warning interrupt */ INT_CAN0_Rx_Warning = 49, /**< CAN0 Rx warning interrupt */ INT_CAN0_Wake_Up = 50, /**< CAN0 wake up interrupt */ INT_I2S0_Tx = 51, /**< I2S0 transmit interrupt */ INT_I2S0_Rx = 52, /**< I2S0 receive interrupt */ INT_CAN1_ORed_Message_buffer = 53, /**< CAN1 OR'd message buffers interrupt */ INT_CAN1_Bus_Off = 54, /**< CAN1 bus off interrupt */ INT_CAN1_Error = 55, /**< CAN1 error interrupt */ INT_CAN1_Tx_Warning = 56, /**< CAN1 Tx warning interrupt */ INT_CAN1_Rx_Warning = 57, /**< CAN1 Rx warning interrupt */ INT_CAN1_Wake_Up = 58, /**< CAN1 wake up interrupt */ INT_Reserved59 = 59, /**< Reserved interrupt 59 */ INT_UART0_LON = 60, /**< UART0 LON interrupt */ INT_UART0_RX_TX = 61, /**< UART0 Receive/Transmit interrupt */ INT_UART0_ERR = 62, /**< UART0 Error interrupt */ INT_UART1_RX_TX = 63, /**< UART1 Receive/Transmit interrupt */ INT_UART1_ERR = 64, /**< UART1 Error interrupt */ INT_UART2_RX_TX = 65, /**< UART2 Receive/Transmit interrupt */ INT_UART2_ERR = 66, /**< UART2 Error interrupt */ INT_UART3_RX_TX = 67, /**< UART3 Receive/Transmit interrupt */ INT_UART3_ERR = 68, /**< UART3 Error interrupt */ INT_UART4_RX_TX = 69, /**< UART4 Receive/Transmit interrupt */ INT_UART4_ERR = 70, /**< UART4 Error interrupt */ INT_UART5_RX_TX = 71, /**< UART5 Receive/Transmit interrupt */ INT_UART5_ERR = 72, /**< UART5 Error interrupt */ INT_ADC0 = 73, /**< ADC0 interrupt */ INT_ADC1 = 74, /**< ADC1 interrupt */ INT_CMP0 = 75, /**< CMP0 interrupt */ INT_CMP1 = 76, /**< CMP1 interrupt */ INT_CMP2 = 77, /**< CMP2 interrupt */ INT_FTM0 = 78, /**< FTM0 fault, overflow and channels interrupt */ INT_FTM1 = 79, /**< FTM1 fault, overflow and channels interrupt */ INT_FTM2 = 80, /**< FTM2 fault, overflow and channels interrupt */ INT_CMT = 81, /**< CMT interrupt */ INT_RTC = 82, /**< RTC interrupt */ INT_RTC_Seconds = 83, /**< RTC seconds interrupt */ INT_PIT0 = 84, /**< PIT timer channel 0 interrupt */ INT_PIT1 = 85, /**< PIT timer channel 1 interrupt */ INT_PIT2 = 86, /**< PIT timer channel 2 interrupt */ INT_PIT3 = 87, /**< PIT timer channel 3 interrupt */ INT_PDB0 = 88, /**< PDB0 Interrupt */ INT_USB0 = 89, /**< USB0 interrupt */ INT_USBDCD = 90, /**< USBDCD Interrupt */ INT_Reserved91 = 91, /**< Reserved interrupt 91 */ INT_Reserved92 = 92, /**< Reserved interrupt 92 */ INT_Reserved93 = 93, /**< Reserved interrupt 93 */ INT_Reserved94 = 94, /**< Reserved interrupt 94 */ INT_Reserved95 = 95, /**< Reserved interrupt 95 */ INT_SDHC = 96, /**< SDHC Interrupt */ INT_DAC0 = 97, /**< DAC0 interrupt */ INT_DAC1 = 98, /**< DAC1 interrupt */ INT_TSI0 = 99, /**< TSI0 Interrupt */ INT_MCG = 100, /**< MCG Interrupt */ INT_LPTimer = 101, /**< LPTimer interrupt */ INT_Reserved102 = 102, /**< Reserved interrupt 102 */ INT_PORTA = 103, /**< Port A interrupt */ INT_PORTB = 104, /**< Port B interrupt */ INT_PORTC = 105, /**< Port C interrupt */ INT_PORTD = 106, /**< Port D interrupt */ INT_PORTE = 107, /**< Port E interrupt */ INT_Reserved108 = 108, /**< Reserved interrupt 108 */ INT_Reserved109 = 109, /**< Reserved interrupt 109 */ INT_SWI = 110, /**< Software interrupt */ INT_Reserved111 = 111, /**< Reserved interrupt 111 */ INT_Reserved112 = 112, /**< Reserved interrupt 112 */ INT_Reserved113 = 113, /**< Reserved interrupt 113 */ INT_Reserved114 = 114, /**< Reserved interrupt 114 */ INT_Reserved115 = 115, /**< Reserved interrupt 115 */ INT_Reserved116 = 116, /**< Reserved interrupt 116 */ INT_Reserved117 = 117, /**< Reserved interrupt 117 */ INT_Reserved118 = 118, /**< Reserved interrupt 118 */ INT_Reserved119 = 119 /**< Reserved interrupt 119 */ } IRQInterruptIndex; /** * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Peripheral type defines ---------------------------------------------------------------------------- */ /** * @addtogroup Peripheral_defines Peripheral type defines * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC ---------------------------------------------------------------------------- */ /** * @addtogroup ADC_Peripheral ADC * @{ */ /** ADC - Peripheral register structure */ typedef struct ADC_MemMap { uint32 SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ uint32 CFG1; /**< ADC configuration register 1, offset: 0x8 */ uint32 CFG2; /**< Configuration register 2, offset: 0xC */ uint32 R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ uint32 CV1; /**< Compare value registers, offset: 0x18 */ uint32 CV2; /**< Compare value registers, offset: 0x1C */ uint32 SC2; /**< Status and control register 2, offset: 0x20 */ uint32 SC3; /**< Status and control register 3, offset: 0x24 */ uint32 OFS; /**< ADC offset correction register, offset: 0x28 */ uint32 PG; /**< ADC plus-side gain register, offset: 0x2C */ uint32 MG; /**< ADC minus-side gain register, offset: 0x30 */ uint32 CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ uint32 CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ uint32 CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ uint32 CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ uint32 CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ uint32 CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ uint32 CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ uint32 PGA; /**< ADC PGA register, offset: 0x50 */ uint32 CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ uint32 CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ uint32 CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ uint32 CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ uint32 CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ uint32 CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ uint32 CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ } volatile *ADC_MemMapPtr; /* ---------------------------------------------------------------------------- -- ADC - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros * @{ */ /* ADC - Register accessors */ #define ADC_SC1_REG(base,index) ((base)->SC1[index]) #define ADC_CFG1_REG(base) ((base)->CFG1) #define ADC_CFG2_REG(base) ((base)->CFG2) #define ADC_R_REG(base,index) ((base)->R[index]) #define ADC_CV1_REG(base) ((base)->CV1) #define ADC_CV2_REG(base) ((base)->CV2) #define ADC_SC2_REG(base) ((base)->SC2) #define ADC_SC3_REG(base) ((base)->SC3) #define ADC_OFS_REG(base) ((base)->OFS) #define ADC_PG_REG(base) ((base)->PG) #define ADC_MG_REG(base) ((base)->MG) #define ADC_CLPD_REG(base) ((base)->CLPD) #define ADC_CLPS_REG(base) ((base)->CLPS) #define ADC_CLP4_REG(base) ((base)->CLP4) #define ADC_CLP3_REG(base) ((base)->CLP3) #define ADC_CLP2_REG(base) ((base)->CLP2) #define ADC_CLP1_REG(base) ((base)->CLP1) #define ADC_CLP0_REG(base) ((base)->CLP0) #define ADC_PGA_REG(base) ((base)->PGA) #define ADC_CLMD_REG(base) ((base)->CLMD) #define ADC_CLMS_REG(base) ((base)->CLMS) #define ADC_CLM4_REG(base) ((base)->CLM4) #define ADC_CLM3_REG(base) ((base)->CLM3) #define ADC_CLM2_REG(base) ((base)->CLM2) #define ADC_CLM1_REG(base) ((base)->CLM1) #define ADC_CLM0_REG(base) ((base)->CLM0) /** * @} */ /* end of group ADC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /* SC1 Bit Fields */ #define ADC_SC1_ADCH_MASK 0x1Fu #define ADC_SC1_ADCH_SHIFT 0 #define ADC_SC1_ADCH(x) (((uint32)(((uint32)(x))<MPRA) #define AIPS_PACRA_REG(base) ((base)->PACRA) #define AIPS_PACRB_REG(base) ((base)->PACRB) #define AIPS_PACRC_REG(base) ((base)->PACRC) #define AIPS_PACRD_REG(base) ((base)->PACRD) #define AIPS_PACRE_REG(base) ((base)->PACRE) #define AIPS_PACRF_REG(base) ((base)->PACRF) #define AIPS_PACRG_REG(base) ((base)->PACRG) #define AIPS_PACRH_REG(base) ((base)->PACRH) #define AIPS_PACRI_REG(base) ((base)->PACRI) #define AIPS_PACRJ_REG(base) ((base)->PACRJ) #define AIPS_PACRK_REG(base) ((base)->PACRK) #define AIPS_PACRL_REG(base) ((base)->PACRL) #define AIPS_PACRM_REG(base) ((base)->PACRM) #define AIPS_PACRN_REG(base) ((base)->PACRN) #define AIPS_PACRO_REG(base) ((base)->PACRO) #define AIPS_PACRP_REG(base) ((base)->PACRP) /** * @} */ /* end of group AIPS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- AIPS Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup AIPS_Register_Masks AIPS Register Masks * @{ */ /* MPRA Bit Fields */ #define AIPS_MPRA_MPL5_MASK 0x100u #define AIPS_MPRA_MPL5_SHIFT 8 #define AIPS_MPRA_MTW5_MASK 0x200u #define AIPS_MPRA_MTW5_SHIFT 9 #define AIPS_MPRA_MTR5_MASK 0x400u #define AIPS_MPRA_MTR5_SHIFT 10 #define AIPS_MPRA_MPL4_MASK 0x1000u #define AIPS_MPRA_MPL4_SHIFT 12 #define AIPS_MPRA_MTW4_MASK 0x2000u #define AIPS_MPRA_MTW4_SHIFT 13 #define AIPS_MPRA_MTR4_MASK 0x4000u #define AIPS_MPRA_MTR4_SHIFT 14 #define AIPS_MPRA_MPL3_MASK 0x10000u #define AIPS_MPRA_MPL3_SHIFT 16 #define AIPS_MPRA_MTW3_MASK 0x20000u #define AIPS_MPRA_MTW3_SHIFT 17 #define AIPS_MPRA_MTR3_MASK 0x40000u #define AIPS_MPRA_MTR3_SHIFT 18 #define AIPS_MPRA_MPL2_MASK 0x100000u #define AIPS_MPRA_MPL2_SHIFT 20 #define AIPS_MPRA_MTW2_MASK 0x200000u #define AIPS_MPRA_MTW2_SHIFT 21 #define AIPS_MPRA_MTR2_MASK 0x400000u #define AIPS_MPRA_MTR2_SHIFT 22 #define AIPS_MPRA_MPL1_MASK 0x1000000u #define AIPS_MPRA_MPL1_SHIFT 24 #define AIPS_MPRA_MTW1_MASK 0x2000000u #define AIPS_MPRA_MTW1_SHIFT 25 #define AIPS_MPRA_MTR1_MASK 0x4000000u #define AIPS_MPRA_MTR1_SHIFT 26 #define AIPS_MPRA_MPL0_MASK 0x10000000u #define AIPS_MPRA_MPL0_SHIFT 28 #define AIPS_MPRA_MTW0_MASK 0x20000000u #define AIPS_MPRA_MTW0_SHIFT 29 #define AIPS_MPRA_MTR0_MASK 0x40000000u #define AIPS_MPRA_MTR0_SHIFT 30 /* PACRA Bit Fields */ #define AIPS_PACRA_TP7_MASK 0x1u #define AIPS_PACRA_TP7_SHIFT 0 #define AIPS_PACRA_WP7_MASK 0x2u #define AIPS_PACRA_WP7_SHIFT 1 #define AIPS_PACRA_SP7_MASK 0x4u #define AIPS_PACRA_SP7_SHIFT 2 #define AIPS_PACRA_TP6_MASK 0x10u #define AIPS_PACRA_TP6_SHIFT 4 #define AIPS_PACRA_WP6_MASK 0x20u #define AIPS_PACRA_WP6_SHIFT 5 #define AIPS_PACRA_SP6_MASK 0x40u #define AIPS_PACRA_SP6_SHIFT 6 #define AIPS_PACRA_TP5_MASK 0x100u #define AIPS_PACRA_TP5_SHIFT 8 #define AIPS_PACRA_WP5_MASK 0x200u #define AIPS_PACRA_WP5_SHIFT 9 #define AIPS_PACRA_SP5_MASK 0x400u #define AIPS_PACRA_SP5_SHIFT 10 #define AIPS_PACRA_TP4_MASK 0x1000u #define AIPS_PACRA_TP4_SHIFT 12 #define AIPS_PACRA_WP4_MASK 0x2000u #define AIPS_PACRA_WP4_SHIFT 13 #define AIPS_PACRA_SP4_MASK 0x4000u #define AIPS_PACRA_SP4_SHIFT 14 #define AIPS_PACRA_TP3_MASK 0x10000u #define AIPS_PACRA_TP3_SHIFT 16 #define AIPS_PACRA_WP3_MASK 0x20000u #define AIPS_PACRA_WP3_SHIFT 17 #define AIPS_PACRA_SP3_MASK 0x40000u #define AIPS_PACRA_SP3_SHIFT 18 #define AIPS_PACRA_TP2_MASK 0x100000u #define AIPS_PACRA_TP2_SHIFT 20 #define AIPS_PACRA_WP2_MASK 0x200000u #define AIPS_PACRA_WP2_SHIFT 21 #define AIPS_PACRA_SP2_MASK 0x400000u #define AIPS_PACRA_SP2_SHIFT 22 #define AIPS_PACRA_TP1_MASK 0x1000000u #define AIPS_PACRA_TP1_SHIFT 24 #define AIPS_PACRA_WP1_MASK 0x2000000u #define AIPS_PACRA_WP1_SHIFT 25 #define AIPS_PACRA_SP1_MASK 0x4000000u #define AIPS_PACRA_SP1_SHIFT 26 #define AIPS_PACRA_TP0_MASK 0x10000000u #define AIPS_PACRA_TP0_SHIFT 28 #define AIPS_PACRA_WP0_MASK 0x20000000u #define AIPS_PACRA_WP0_SHIFT 29 #define AIPS_PACRA_SP0_MASK 0x40000000u #define AIPS_PACRA_SP0_SHIFT 30 /* PACRB Bit Fields */ #define AIPS_PACRB_TP7_MASK 0x1u #define AIPS_PACRB_TP7_SHIFT 0 #define AIPS_PACRB_WP7_MASK 0x2u #define AIPS_PACRB_WP7_SHIFT 1 #define AIPS_PACRB_SP7_MASK 0x4u #define AIPS_PACRB_SP7_SHIFT 2 #define AIPS_PACRB_TP6_MASK 0x10u #define AIPS_PACRB_TP6_SHIFT 4 #define AIPS_PACRB_WP6_MASK 0x20u #define AIPS_PACRB_WP6_SHIFT 5 #define AIPS_PACRB_SP6_MASK 0x40u #define AIPS_PACRB_SP6_SHIFT 6 #define AIPS_PACRB_TP5_MASK 0x100u #define AIPS_PACRB_TP5_SHIFT 8 #define AIPS_PACRB_WP5_MASK 0x200u #define AIPS_PACRB_WP5_SHIFT 9 #define AIPS_PACRB_SP5_MASK 0x400u #define AIPS_PACRB_SP5_SHIFT 10 #define AIPS_PACRB_TP4_MASK 0x1000u #define AIPS_PACRB_TP4_SHIFT 12 #define AIPS_PACRB_WP4_MASK 0x2000u #define AIPS_PACRB_WP4_SHIFT 13 #define AIPS_PACRB_SP4_MASK 0x4000u #define AIPS_PACRB_SP4_SHIFT 14 #define AIPS_PACRB_TP3_MASK 0x10000u #define AIPS_PACRB_TP3_SHIFT 16 #define AIPS_PACRB_WP3_MASK 0x20000u #define AIPS_PACRB_WP3_SHIFT 17 #define AIPS_PACRB_SP3_MASK 0x40000u #define AIPS_PACRB_SP3_SHIFT 18 #define AIPS_PACRB_TP2_MASK 0x100000u #define AIPS_PACRB_TP2_SHIFT 20 #define AIPS_PACRB_WP2_MASK 0x200000u #define AIPS_PACRB_WP2_SHIFT 21 #define AIPS_PACRB_SP2_MASK 0x400000u #define AIPS_PACRB_SP2_SHIFT 22 #define AIPS_PACRB_TP1_MASK 0x1000000u #define AIPS_PACRB_TP1_SHIFT 24 #define AIPS_PACRB_WP1_MASK 0x2000000u #define AIPS_PACRB_WP1_SHIFT 25 #define AIPS_PACRB_SP1_MASK 0x4000000u #define AIPS_PACRB_SP1_SHIFT 26 #define AIPS_PACRB_TP0_MASK 0x10000000u #define AIPS_PACRB_TP0_SHIFT 28 #define AIPS_PACRB_WP0_MASK 0x20000000u #define AIPS_PACRB_WP0_SHIFT 29 #define AIPS_PACRB_SP0_MASK 0x40000000u #define AIPS_PACRB_SP0_SHIFT 30 /* PACRC Bit Fields */ #define AIPS_PACRC_TP7_MASK 0x1u #define AIPS_PACRC_TP7_SHIFT 0 #define AIPS_PACRC_WP7_MASK 0x2u #define AIPS_PACRC_WP7_SHIFT 1 #define AIPS_PACRC_SP7_MASK 0x4u #define AIPS_PACRC_SP7_SHIFT 2 #define AIPS_PACRC_TP6_MASK 0x10u #define AIPS_PACRC_TP6_SHIFT 4 #define AIPS_PACRC_WP6_MASK 0x20u #define AIPS_PACRC_WP6_SHIFT 5 #define AIPS_PACRC_SP6_MASK 0x40u #define AIPS_PACRC_SP6_SHIFT 6 #define AIPS_PACRC_TP5_MASK 0x100u #define AIPS_PACRC_TP5_SHIFT 8 #define AIPS_PACRC_WP5_MASK 0x200u #define AIPS_PACRC_WP5_SHIFT 9 #define AIPS_PACRC_SP5_MASK 0x400u #define AIPS_PACRC_SP5_SHIFT 10 #define AIPS_PACRC_TP4_MASK 0x1000u #define AIPS_PACRC_TP4_SHIFT 12 #define AIPS_PACRC_WP4_MASK 0x2000u #define AIPS_PACRC_WP4_SHIFT 13 #define AIPS_PACRC_SP4_MASK 0x4000u #define AIPS_PACRC_SP4_SHIFT 14 #define AIPS_PACRC_TP3_MASK 0x10000u #define AIPS_PACRC_TP3_SHIFT 16 #define AIPS_PACRC_WP3_MASK 0x20000u #define AIPS_PACRC_WP3_SHIFT 17 #define AIPS_PACRC_SP3_MASK 0x40000u #define AIPS_PACRC_SP3_SHIFT 18 #define AIPS_PACRC_TP2_MASK 0x100000u #define AIPS_PACRC_TP2_SHIFT 20 #define AIPS_PACRC_WP2_MASK 0x200000u #define AIPS_PACRC_WP2_SHIFT 21 #define AIPS_PACRC_SP2_MASK 0x400000u #define AIPS_PACRC_SP2_SHIFT 22 #define AIPS_PACRC_TP1_MASK 0x1000000u #define AIPS_PACRC_TP1_SHIFT 24 #define AIPS_PACRC_WP1_MASK 0x2000000u #define AIPS_PACRC_WP1_SHIFT 25 #define AIPS_PACRC_SP1_MASK 0x4000000u #define AIPS_PACRC_SP1_SHIFT 26 #define AIPS_PACRC_TP0_MASK 0x10000000u #define AIPS_PACRC_TP0_SHIFT 28 #define AIPS_PACRC_WP0_MASK 0x20000000u #define AIPS_PACRC_WP0_SHIFT 29 #define AIPS_PACRC_SP0_MASK 0x40000000u #define AIPS_PACRC_SP0_SHIFT 30 /* PACRD Bit Fields */ #define AIPS_PACRD_TP7_MASK 0x1u #define AIPS_PACRD_TP7_SHIFT 0 #define AIPS_PACRD_WP7_MASK 0x2u #define AIPS_PACRD_WP7_SHIFT 1 #define AIPS_PACRD_SP7_MASK 0x4u #define AIPS_PACRD_SP7_SHIFT 2 #define AIPS_PACRD_TP6_MASK 0x10u #define AIPS_PACRD_TP6_SHIFT 4 #define AIPS_PACRD_WP6_MASK 0x20u #define AIPS_PACRD_WP6_SHIFT 5 #define AIPS_PACRD_SP6_MASK 0x40u #define AIPS_PACRD_SP6_SHIFT 6 #define AIPS_PACRD_TP5_MASK 0x100u #define AIPS_PACRD_TP5_SHIFT 8 #define AIPS_PACRD_WP5_MASK 0x200u #define AIPS_PACRD_WP5_SHIFT 9 #define AIPS_PACRD_SP5_MASK 0x400u #define AIPS_PACRD_SP5_SHIFT 10 #define AIPS_PACRD_TP4_MASK 0x1000u #define AIPS_PACRD_TP4_SHIFT 12 #define AIPS_PACRD_WP4_MASK 0x2000u #define AIPS_PACRD_WP4_SHIFT 13 #define AIPS_PACRD_SP4_MASK 0x4000u #define AIPS_PACRD_SP4_SHIFT 14 #define AIPS_PACRD_TP3_MASK 0x10000u #define AIPS_PACRD_TP3_SHIFT 16 #define AIPS_PACRD_WP3_MASK 0x20000u #define AIPS_PACRD_WP3_SHIFT 17 #define AIPS_PACRD_SP3_MASK 0x40000u #define AIPS_PACRD_SP3_SHIFT 18 #define AIPS_PACRD_TP2_MASK 0x100000u #define AIPS_PACRD_TP2_SHIFT 20 #define AIPS_PACRD_WP2_MASK 0x200000u #define AIPS_PACRD_WP2_SHIFT 21 #define AIPS_PACRD_SP2_MASK 0x400000u #define AIPS_PACRD_SP2_SHIFT 22 #define AIPS_PACRD_TP1_MASK 0x1000000u #define AIPS_PACRD_TP1_SHIFT 24 #define AIPS_PACRD_WP1_MASK 0x2000000u #define AIPS_PACRD_WP1_SHIFT 25 #define AIPS_PACRD_SP1_MASK 0x4000000u #define AIPS_PACRD_SP1_SHIFT 26 #define AIPS_PACRD_TP0_MASK 0x10000000u #define AIPS_PACRD_TP0_SHIFT 28 #define AIPS_PACRD_WP0_MASK 0x20000000u #define AIPS_PACRD_WP0_SHIFT 29 #define AIPS_PACRD_SP0_MASK 0x40000000u #define AIPS_PACRD_SP0_SHIFT 30 /* PACRE Bit Fields */ #define AIPS_PACRE_TP7_MASK 0x1u #define AIPS_PACRE_TP7_SHIFT 0 #define AIPS_PACRE_WP7_MASK 0x2u #define AIPS_PACRE_WP7_SHIFT 1 #define AIPS_PACRE_SP7_MASK 0x4u #define AIPS_PACRE_SP7_SHIFT 2 #define AIPS_PACRE_TP6_MASK 0x10u #define AIPS_PACRE_TP6_SHIFT 4 #define AIPS_PACRE_WP6_MASK 0x20u #define AIPS_PACRE_WP6_SHIFT 5 #define AIPS_PACRE_SP6_MASK 0x40u #define AIPS_PACRE_SP6_SHIFT 6 #define AIPS_PACRE_TP5_MASK 0x100u #define AIPS_PACRE_TP5_SHIFT 8 #define AIPS_PACRE_WP5_MASK 0x200u #define AIPS_PACRE_WP5_SHIFT 9 #define AIPS_PACRE_SP5_MASK 0x400u #define AIPS_PACRE_SP5_SHIFT 10 #define AIPS_PACRE_TP4_MASK 0x1000u #define AIPS_PACRE_TP4_SHIFT 12 #define AIPS_PACRE_WP4_MASK 0x2000u #define AIPS_PACRE_WP4_SHIFT 13 #define AIPS_PACRE_SP4_MASK 0x4000u #define AIPS_PACRE_SP4_SHIFT 14 #define AIPS_PACRE_TP3_MASK 0x10000u #define AIPS_PACRE_TP3_SHIFT 16 #define AIPS_PACRE_WP3_MASK 0x20000u #define AIPS_PACRE_WP3_SHIFT 17 #define AIPS_PACRE_SP3_MASK 0x40000u #define AIPS_PACRE_SP3_SHIFT 18 #define AIPS_PACRE_TP2_MASK 0x100000u #define AIPS_PACRE_TP2_SHIFT 20 #define AIPS_PACRE_WP2_MASK 0x200000u #define AIPS_PACRE_WP2_SHIFT 21 #define AIPS_PACRE_SP2_MASK 0x400000u #define AIPS_PACRE_SP2_SHIFT 22 #define AIPS_PACRE_TP1_MASK 0x1000000u #define AIPS_PACRE_TP1_SHIFT 24 #define AIPS_PACRE_WP1_MASK 0x2000000u #define AIPS_PACRE_WP1_SHIFT 25 #define AIPS_PACRE_SP1_MASK 0x4000000u #define AIPS_PACRE_SP1_SHIFT 26 #define AIPS_PACRE_TP0_MASK 0x10000000u #define AIPS_PACRE_TP0_SHIFT 28 #define AIPS_PACRE_WP0_MASK 0x20000000u #define AIPS_PACRE_WP0_SHIFT 29 #define AIPS_PACRE_SP0_MASK 0x40000000u #define AIPS_PACRE_SP0_SHIFT 30 /* PACRF Bit Fields */ #define AIPS_PACRF_TP7_MASK 0x1u #define AIPS_PACRF_TP7_SHIFT 0 #define AIPS_PACRF_WP7_MASK 0x2u #define AIPS_PACRF_WP7_SHIFT 1 #define AIPS_PACRF_SP7_MASK 0x4u #define AIPS_PACRF_SP7_SHIFT 2 #define AIPS_PACRF_TP6_MASK 0x10u #define AIPS_PACRF_TP6_SHIFT 4 #define AIPS_PACRF_WP6_MASK 0x20u #define AIPS_PACRF_WP6_SHIFT 5 #define AIPS_PACRF_SP6_MASK 0x40u #define AIPS_PACRF_SP6_SHIFT 6 #define AIPS_PACRF_TP5_MASK 0x100u #define AIPS_PACRF_TP5_SHIFT 8 #define AIPS_PACRF_WP5_MASK 0x200u #define AIPS_PACRF_WP5_SHIFT 9 #define AIPS_PACRF_SP5_MASK 0x400u #define AIPS_PACRF_SP5_SHIFT 10 #define AIPS_PACRF_TP4_MASK 0x1000u #define AIPS_PACRF_TP4_SHIFT 12 #define AIPS_PACRF_WP4_MASK 0x2000u #define AIPS_PACRF_WP4_SHIFT 13 #define AIPS_PACRF_SP4_MASK 0x4000u #define AIPS_PACRF_SP4_SHIFT 14 #define AIPS_PACRF_TP3_MASK 0x10000u #define AIPS_PACRF_TP3_SHIFT 16 #define AIPS_PACRF_WP3_MASK 0x20000u #define AIPS_PACRF_WP3_SHIFT 17 #define AIPS_PACRF_SP3_MASK 0x40000u #define AIPS_PACRF_SP3_SHIFT 18 #define AIPS_PACRF_TP2_MASK 0x100000u #define AIPS_PACRF_TP2_SHIFT 20 #define AIPS_PACRF_WP2_MASK 0x200000u #define AIPS_PACRF_WP2_SHIFT 21 #define AIPS_PACRF_SP2_MASK 0x400000u #define AIPS_PACRF_SP2_SHIFT 22 #define AIPS_PACRF_TP1_MASK 0x1000000u #define AIPS_PACRF_TP1_SHIFT 24 #define AIPS_PACRF_WP1_MASK 0x2000000u #define AIPS_PACRF_WP1_SHIFT 25 #define AIPS_PACRF_SP1_MASK 0x4000000u #define AIPS_PACRF_SP1_SHIFT 26 #define AIPS_PACRF_TP0_MASK 0x10000000u #define AIPS_PACRF_TP0_SHIFT 28 #define AIPS_PACRF_WP0_MASK 0x20000000u #define AIPS_PACRF_WP0_SHIFT 29 #define AIPS_PACRF_SP0_MASK 0x40000000u #define AIPS_PACRF_SP0_SHIFT 30 /* PACRG Bit Fields */ #define AIPS_PACRG_TP7_MASK 0x1u #define AIPS_PACRG_TP7_SHIFT 0 #define AIPS_PACRG_WP7_MASK 0x2u #define AIPS_PACRG_WP7_SHIFT 1 #define AIPS_PACRG_SP7_MASK 0x4u #define AIPS_PACRG_SP7_SHIFT 2 #define AIPS_PACRG_TP6_MASK 0x10u #define AIPS_PACRG_TP6_SHIFT 4 #define AIPS_PACRG_WP6_MASK 0x20u #define AIPS_PACRG_WP6_SHIFT 5 #define AIPS_PACRG_SP6_MASK 0x40u #define AIPS_PACRG_SP6_SHIFT 6 #define AIPS_PACRG_TP5_MASK 0x100u #define AIPS_PACRG_TP5_SHIFT 8 #define AIPS_PACRG_WP5_MASK 0x200u #define AIPS_PACRG_WP5_SHIFT 9 #define AIPS_PACRG_SP5_MASK 0x400u #define AIPS_PACRG_SP5_SHIFT 10 #define AIPS_PACRG_TP4_MASK 0x1000u #define AIPS_PACRG_TP4_SHIFT 12 #define AIPS_PACRG_WP4_MASK 0x2000u #define AIPS_PACRG_WP4_SHIFT 13 #define AIPS_PACRG_SP4_MASK 0x4000u #define AIPS_PACRG_SP4_SHIFT 14 #define AIPS_PACRG_TP3_MASK 0x10000u #define AIPS_PACRG_TP3_SHIFT 16 #define AIPS_PACRG_WP3_MASK 0x20000u #define AIPS_PACRG_WP3_SHIFT 17 #define AIPS_PACRG_SP3_MASK 0x40000u #define AIPS_PACRG_SP3_SHIFT 18 #define AIPS_PACRG_TP2_MASK 0x100000u #define AIPS_PACRG_TP2_SHIFT 20 #define AIPS_PACRG_WP2_MASK 0x200000u #define AIPS_PACRG_WP2_SHIFT 21 #define AIPS_PACRG_SP2_MASK 0x400000u #define AIPS_PACRG_SP2_SHIFT 22 #define AIPS_PACRG_TP1_MASK 0x1000000u #define AIPS_PACRG_TP1_SHIFT 24 #define AIPS_PACRG_WP1_MASK 0x2000000u #define AIPS_PACRG_WP1_SHIFT 25 #define AIPS_PACRG_SP1_MASK 0x4000000u #define AIPS_PACRG_SP1_SHIFT 26 #define AIPS_PACRG_TP0_MASK 0x10000000u #define AIPS_PACRG_TP0_SHIFT 28 #define AIPS_PACRG_WP0_MASK 0x20000000u #define AIPS_PACRG_WP0_SHIFT 29 #define AIPS_PACRG_SP0_MASK 0x40000000u #define AIPS_PACRG_SP0_SHIFT 30 /* PACRH Bit Fields */ #define AIPS_PACRH_TP7_MASK 0x1u #define AIPS_PACRH_TP7_SHIFT 0 #define AIPS_PACRH_WP7_MASK 0x2u #define AIPS_PACRH_WP7_SHIFT 1 #define AIPS_PACRH_SP7_MASK 0x4u #define AIPS_PACRH_SP7_SHIFT 2 #define AIPS_PACRH_TP6_MASK 0x10u #define AIPS_PACRH_TP6_SHIFT 4 #define AIPS_PACRH_WP6_MASK 0x20u #define AIPS_PACRH_WP6_SHIFT 5 #define AIPS_PACRH_SP6_MASK 0x40u #define AIPS_PACRH_SP6_SHIFT 6 #define AIPS_PACRH_TP5_MASK 0x100u #define AIPS_PACRH_TP5_SHIFT 8 #define AIPS_PACRH_WP5_MASK 0x200u #define AIPS_PACRH_WP5_SHIFT 9 #define AIPS_PACRH_SP5_MASK 0x400u #define AIPS_PACRH_SP5_SHIFT 10 #define AIPS_PACRH_TP4_MASK 0x1000u #define AIPS_PACRH_TP4_SHIFT 12 #define AIPS_PACRH_WP4_MASK 0x2000u #define AIPS_PACRH_WP4_SHIFT 13 #define AIPS_PACRH_SP4_MASK 0x4000u #define AIPS_PACRH_SP4_SHIFT 14 #define AIPS_PACRH_TP3_MASK 0x10000u #define AIPS_PACRH_TP3_SHIFT 16 #define AIPS_PACRH_WP3_MASK 0x20000u #define AIPS_PACRH_WP3_SHIFT 17 #define AIPS_PACRH_SP3_MASK 0x40000u #define AIPS_PACRH_SP3_SHIFT 18 #define AIPS_PACRH_TP2_MASK 0x100000u #define AIPS_PACRH_TP2_SHIFT 20 #define AIPS_PACRH_WP2_MASK 0x200000u #define AIPS_PACRH_WP2_SHIFT 21 #define AIPS_PACRH_SP2_MASK 0x400000u #define AIPS_PACRH_SP2_SHIFT 22 #define AIPS_PACRH_TP1_MASK 0x1000000u #define AIPS_PACRH_TP1_SHIFT 24 #define AIPS_PACRH_WP1_MASK 0x2000000u #define AIPS_PACRH_WP1_SHIFT 25 #define AIPS_PACRH_SP1_MASK 0x4000000u #define AIPS_PACRH_SP1_SHIFT 26 #define AIPS_PACRH_TP0_MASK 0x10000000u #define AIPS_PACRH_TP0_SHIFT 28 #define AIPS_PACRH_WP0_MASK 0x20000000u #define AIPS_PACRH_WP0_SHIFT 29 #define AIPS_PACRH_SP0_MASK 0x40000000u #define AIPS_PACRH_SP0_SHIFT 30 /* PACRI Bit Fields */ #define AIPS_PACRI_TP7_MASK 0x1u #define AIPS_PACRI_TP7_SHIFT 0 #define AIPS_PACRI_WP7_MASK 0x2u #define AIPS_PACRI_WP7_SHIFT 1 #define AIPS_PACRI_SP7_MASK 0x4u #define AIPS_PACRI_SP7_SHIFT 2 #define AIPS_PACRI_TP6_MASK 0x10u #define AIPS_PACRI_TP6_SHIFT 4 #define AIPS_PACRI_WP6_MASK 0x20u #define AIPS_PACRI_WP6_SHIFT 5 #define AIPS_PACRI_SP6_MASK 0x40u #define AIPS_PACRI_SP6_SHIFT 6 #define AIPS_PACRI_TP5_MASK 0x100u #define AIPS_PACRI_TP5_SHIFT 8 #define AIPS_PACRI_WP5_MASK 0x200u #define AIPS_PACRI_WP5_SHIFT 9 #define AIPS_PACRI_SP5_MASK 0x400u #define AIPS_PACRI_SP5_SHIFT 10 #define AIPS_PACRI_TP4_MASK 0x1000u #define AIPS_PACRI_TP4_SHIFT 12 #define AIPS_PACRI_WP4_MASK 0x2000u #define AIPS_PACRI_WP4_SHIFT 13 #define AIPS_PACRI_SP4_MASK 0x4000u #define AIPS_PACRI_SP4_SHIFT 14 #define AIPS_PACRI_TP3_MASK 0x10000u #define AIPS_PACRI_TP3_SHIFT 16 #define AIPS_PACRI_WP3_MASK 0x20000u #define AIPS_PACRI_WP3_SHIFT 17 #define AIPS_PACRI_SP3_MASK 0x40000u #define AIPS_PACRI_SP3_SHIFT 18 #define AIPS_PACRI_TP2_MASK 0x100000u #define AIPS_PACRI_TP2_SHIFT 20 #define AIPS_PACRI_WP2_MASK 0x200000u #define AIPS_PACRI_WP2_SHIFT 21 #define AIPS_PACRI_SP2_MASK 0x400000u #define AIPS_PACRI_SP2_SHIFT 22 #define AIPS_PACRI_TP1_MASK 0x1000000u #define AIPS_PACRI_TP1_SHIFT 24 #define AIPS_PACRI_WP1_MASK 0x2000000u #define AIPS_PACRI_WP1_SHIFT 25 #define AIPS_PACRI_SP1_MASK 0x4000000u #define AIPS_PACRI_SP1_SHIFT 26 #define AIPS_PACRI_TP0_MASK 0x10000000u #define AIPS_PACRI_TP0_SHIFT 28 #define AIPS_PACRI_WP0_MASK 0x20000000u #define AIPS_PACRI_WP0_SHIFT 29 #define AIPS_PACRI_SP0_MASK 0x40000000u #define AIPS_PACRI_SP0_SHIFT 30 /* PACRJ Bit Fields */ #define AIPS_PACRJ_TP7_MASK 0x1u #define AIPS_PACRJ_TP7_SHIFT 0 #define AIPS_PACRJ_WP7_MASK 0x2u #define AIPS_PACRJ_WP7_SHIFT 1 #define AIPS_PACRJ_SP7_MASK 0x4u #define AIPS_PACRJ_SP7_SHIFT 2 #define AIPS_PACRJ_TP6_MASK 0x10u #define AIPS_PACRJ_TP6_SHIFT 4 #define AIPS_PACRJ_WP6_MASK 0x20u #define AIPS_PACRJ_WP6_SHIFT 5 #define AIPS_PACRJ_SP6_MASK 0x40u #define AIPS_PACRJ_SP6_SHIFT 6 #define AIPS_PACRJ_TP5_MASK 0x100u #define AIPS_PACRJ_TP5_SHIFT 8 #define AIPS_PACRJ_WP5_MASK 0x200u #define AIPS_PACRJ_WP5_SHIFT 9 #define AIPS_PACRJ_SP5_MASK 0x400u #define AIPS_PACRJ_SP5_SHIFT 10 #define AIPS_PACRJ_TP4_MASK 0x1000u #define AIPS_PACRJ_TP4_SHIFT 12 #define AIPS_PACRJ_WP4_MASK 0x2000u #define AIPS_PACRJ_WP4_SHIFT 13 #define AIPS_PACRJ_SP4_MASK 0x4000u #define AIPS_PACRJ_SP4_SHIFT 14 #define AIPS_PACRJ_TP3_MASK 0x10000u #define AIPS_PACRJ_TP3_SHIFT 16 #define AIPS_PACRJ_WP3_MASK 0x20000u #define AIPS_PACRJ_WP3_SHIFT 17 #define AIPS_PACRJ_SP3_MASK 0x40000u #define AIPS_PACRJ_SP3_SHIFT 18 #define AIPS_PACRJ_TP2_MASK 0x100000u #define AIPS_PACRJ_TP2_SHIFT 20 #define AIPS_PACRJ_WP2_MASK 0x200000u #define AIPS_PACRJ_WP2_SHIFT 21 #define AIPS_PACRJ_SP2_MASK 0x400000u #define AIPS_PACRJ_SP2_SHIFT 22 #define AIPS_PACRJ_TP1_MASK 0x1000000u #define AIPS_PACRJ_TP1_SHIFT 24 #define AIPS_PACRJ_WP1_MASK 0x2000000u #define AIPS_PACRJ_WP1_SHIFT 25 #define AIPS_PACRJ_SP1_MASK 0x4000000u #define AIPS_PACRJ_SP1_SHIFT 26 #define AIPS_PACRJ_TP0_MASK 0x10000000u #define AIPS_PACRJ_TP0_SHIFT 28 #define AIPS_PACRJ_WP0_MASK 0x20000000u #define AIPS_PACRJ_WP0_SHIFT 29 #define AIPS_PACRJ_SP0_MASK 0x40000000u #define AIPS_PACRJ_SP0_SHIFT 30 /* PACRK Bit Fields */ #define AIPS_PACRK_TP7_MASK 0x1u #define AIPS_PACRK_TP7_SHIFT 0 #define AIPS_PACRK_WP7_MASK 0x2u #define AIPS_PACRK_WP7_SHIFT 1 #define AIPS_PACRK_SP7_MASK 0x4u #define AIPS_PACRK_SP7_SHIFT 2 #define AIPS_PACRK_TP6_MASK 0x10u #define AIPS_PACRK_TP6_SHIFT 4 #define AIPS_PACRK_WP6_MASK 0x20u #define AIPS_PACRK_WP6_SHIFT 5 #define AIPS_PACRK_SP6_MASK 0x40u #define AIPS_PACRK_SP6_SHIFT 6 #define AIPS_PACRK_TP5_MASK 0x100u #define AIPS_PACRK_TP5_SHIFT 8 #define AIPS_PACRK_WP5_MASK 0x200u #define AIPS_PACRK_WP5_SHIFT 9 #define AIPS_PACRK_SP5_MASK 0x400u #define AIPS_PACRK_SP5_SHIFT 10 #define AIPS_PACRK_TP4_MASK 0x1000u #define AIPS_PACRK_TP4_SHIFT 12 #define AIPS_PACRK_WP4_MASK 0x2000u #define AIPS_PACRK_WP4_SHIFT 13 #define AIPS_PACRK_SP4_MASK 0x4000u #define AIPS_PACRK_SP4_SHIFT 14 #define AIPS_PACRK_TP3_MASK 0x10000u #define AIPS_PACRK_TP3_SHIFT 16 #define AIPS_PACRK_WP3_MASK 0x20000u #define AIPS_PACRK_WP3_SHIFT 17 #define AIPS_PACRK_SP3_MASK 0x40000u #define AIPS_PACRK_SP3_SHIFT 18 #define AIPS_PACRK_TP2_MASK 0x100000u #define AIPS_PACRK_TP2_SHIFT 20 #define AIPS_PACRK_WP2_MASK 0x200000u #define AIPS_PACRK_WP2_SHIFT 21 #define AIPS_PACRK_SP2_MASK 0x400000u #define AIPS_PACRK_SP2_SHIFT 22 #define AIPS_PACRK_TP1_MASK 0x1000000u #define AIPS_PACRK_TP1_SHIFT 24 #define AIPS_PACRK_WP1_MASK 0x2000000u #define AIPS_PACRK_WP1_SHIFT 25 #define AIPS_PACRK_SP1_MASK 0x4000000u #define AIPS_PACRK_SP1_SHIFT 26 #define AIPS_PACRK_TP0_MASK 0x10000000u #define AIPS_PACRK_TP0_SHIFT 28 #define AIPS_PACRK_WP0_MASK 0x20000000u #define AIPS_PACRK_WP0_SHIFT 29 #define AIPS_PACRK_SP0_MASK 0x40000000u #define AIPS_PACRK_SP0_SHIFT 30 /* PACRL Bit Fields */ #define AIPS_PACRL_TP7_MASK 0x1u #define AIPS_PACRL_TP7_SHIFT 0 #define AIPS_PACRL_WP7_MASK 0x2u #define AIPS_PACRL_WP7_SHIFT 1 #define AIPS_PACRL_SP7_MASK 0x4u #define AIPS_PACRL_SP7_SHIFT 2 #define AIPS_PACRL_TP6_MASK 0x10u #define AIPS_PACRL_TP6_SHIFT 4 #define AIPS_PACRL_WP6_MASK 0x20u #define AIPS_PACRL_WP6_SHIFT 5 #define AIPS_PACRL_SP6_MASK 0x40u #define AIPS_PACRL_SP6_SHIFT 6 #define AIPS_PACRL_TP5_MASK 0x100u #define AIPS_PACRL_TP5_SHIFT 8 #define AIPS_PACRL_WP5_MASK 0x200u #define AIPS_PACRL_WP5_SHIFT 9 #define AIPS_PACRL_SP5_MASK 0x400u #define AIPS_PACRL_SP5_SHIFT 10 #define AIPS_PACRL_TP4_MASK 0x1000u #define AIPS_PACRL_TP4_SHIFT 12 #define AIPS_PACRL_WP4_MASK 0x2000u #define AIPS_PACRL_WP4_SHIFT 13 #define AIPS_PACRL_SP4_MASK 0x4000u #define AIPS_PACRL_SP4_SHIFT 14 #define AIPS_PACRL_TP3_MASK 0x10000u #define AIPS_PACRL_TP3_SHIFT 16 #define AIPS_PACRL_WP3_MASK 0x20000u #define AIPS_PACRL_WP3_SHIFT 17 #define AIPS_PACRL_SP3_MASK 0x40000u #define AIPS_PACRL_SP3_SHIFT 18 #define AIPS_PACRL_TP2_MASK 0x100000u #define AIPS_PACRL_TP2_SHIFT 20 #define AIPS_PACRL_WP2_MASK 0x200000u #define AIPS_PACRL_WP2_SHIFT 21 #define AIPS_PACRL_SP2_MASK 0x400000u #define AIPS_PACRL_SP2_SHIFT 22 #define AIPS_PACRL_TP1_MASK 0x1000000u #define AIPS_PACRL_TP1_SHIFT 24 #define AIPS_PACRL_WP1_MASK 0x2000000u #define AIPS_PACRL_WP1_SHIFT 25 #define AIPS_PACRL_SP1_MASK 0x4000000u #define AIPS_PACRL_SP1_SHIFT 26 #define AIPS_PACRL_TP0_MASK 0x10000000u #define AIPS_PACRL_TP0_SHIFT 28 #define AIPS_PACRL_WP0_MASK 0x20000000u #define AIPS_PACRL_WP0_SHIFT 29 #define AIPS_PACRL_SP0_MASK 0x40000000u #define AIPS_PACRL_SP0_SHIFT 30 /* PACRM Bit Fields */ #define AIPS_PACRM_TP7_MASK 0x1u #define AIPS_PACRM_TP7_SHIFT 0 #define AIPS_PACRM_WP7_MASK 0x2u #define AIPS_PACRM_WP7_SHIFT 1 #define AIPS_PACRM_SP7_MASK 0x4u #define AIPS_PACRM_SP7_SHIFT 2 #define AIPS_PACRM_TP6_MASK 0x10u #define AIPS_PACRM_TP6_SHIFT 4 #define AIPS_PACRM_WP6_MASK 0x20u #define AIPS_PACRM_WP6_SHIFT 5 #define AIPS_PACRM_SP6_MASK 0x40u #define AIPS_PACRM_SP6_SHIFT 6 #define AIPS_PACRM_TP5_MASK 0x100u #define AIPS_PACRM_TP5_SHIFT 8 #define AIPS_PACRM_WP5_MASK 0x200u #define AIPS_PACRM_WP5_SHIFT 9 #define AIPS_PACRM_SP5_MASK 0x400u #define AIPS_PACRM_SP5_SHIFT 10 #define AIPS_PACRM_TP4_MASK 0x1000u #define AIPS_PACRM_TP4_SHIFT 12 #define AIPS_PACRM_WP4_MASK 0x2000u #define AIPS_PACRM_WP4_SHIFT 13 #define AIPS_PACRM_SP4_MASK 0x4000u #define AIPS_PACRM_SP4_SHIFT 14 #define AIPS_PACRM_TP3_MASK 0x10000u #define AIPS_PACRM_TP3_SHIFT 16 #define AIPS_PACRM_WP3_MASK 0x20000u #define AIPS_PACRM_WP3_SHIFT 17 #define AIPS_PACRM_SP3_MASK 0x40000u #define AIPS_PACRM_SP3_SHIFT 18 #define AIPS_PACRM_TP2_MASK 0x100000u #define AIPS_PACRM_TP2_SHIFT 20 #define AIPS_PACRM_WP2_MASK 0x200000u #define AIPS_PACRM_WP2_SHIFT 21 #define AIPS_PACRM_SP2_MASK 0x400000u #define AIPS_PACRM_SP2_SHIFT 22 #define AIPS_PACRM_TP1_MASK 0x1000000u #define AIPS_PACRM_TP1_SHIFT 24 #define AIPS_PACRM_WP1_MASK 0x2000000u #define AIPS_PACRM_WP1_SHIFT 25 #define AIPS_PACRM_SP1_MASK 0x4000000u #define AIPS_PACRM_SP1_SHIFT 26 #define AIPS_PACRM_TP0_MASK 0x10000000u #define AIPS_PACRM_TP0_SHIFT 28 #define AIPS_PACRM_WP0_MASK 0x20000000u #define AIPS_PACRM_WP0_SHIFT 29 #define AIPS_PACRM_SP0_MASK 0x40000000u #define AIPS_PACRM_SP0_SHIFT 30 /* PACRN Bit Fields */ #define AIPS_PACRN_TP7_MASK 0x1u #define AIPS_PACRN_TP7_SHIFT 0 #define AIPS_PACRN_WP7_MASK 0x2u #define AIPS_PACRN_WP7_SHIFT 1 #define AIPS_PACRN_SP7_MASK 0x4u #define AIPS_PACRN_SP7_SHIFT 2 #define AIPS_PACRN_TP6_MASK 0x10u #define AIPS_PACRN_TP6_SHIFT 4 #define AIPS_PACRN_WP6_MASK 0x20u #define AIPS_PACRN_WP6_SHIFT 5 #define AIPS_PACRN_SP6_MASK 0x40u #define AIPS_PACRN_SP6_SHIFT 6 #define AIPS_PACRN_TP5_MASK 0x100u #define AIPS_PACRN_TP5_SHIFT 8 #define AIPS_PACRN_WP5_MASK 0x200u #define AIPS_PACRN_WP5_SHIFT 9 #define AIPS_PACRN_SP5_MASK 0x400u #define AIPS_PACRN_SP5_SHIFT 10 #define AIPS_PACRN_TP4_MASK 0x1000u #define AIPS_PACRN_TP4_SHIFT 12 #define AIPS_PACRN_WP4_MASK 0x2000u #define AIPS_PACRN_WP4_SHIFT 13 #define AIPS_PACRN_SP4_MASK 0x4000u #define AIPS_PACRN_SP4_SHIFT 14 #define AIPS_PACRN_TP3_MASK 0x10000u #define AIPS_PACRN_TP3_SHIFT 16 #define AIPS_PACRN_WP3_MASK 0x20000u #define AIPS_PACRN_WP3_SHIFT 17 #define AIPS_PACRN_SP3_MASK 0x40000u #define AIPS_PACRN_SP3_SHIFT 18 #define AIPS_PACRN_TP2_MASK 0x100000u #define AIPS_PACRN_TP2_SHIFT 20 #define AIPS_PACRN_WP2_MASK 0x200000u #define AIPS_PACRN_WP2_SHIFT 21 #define AIPS_PACRN_SP2_MASK 0x400000u #define AIPS_PACRN_SP2_SHIFT 22 #define AIPS_PACRN_TP1_MASK 0x1000000u #define AIPS_PACRN_TP1_SHIFT 24 #define AIPS_PACRN_WP1_MASK 0x2000000u #define AIPS_PACRN_WP1_SHIFT 25 #define AIPS_PACRN_SP1_MASK 0x4000000u #define AIPS_PACRN_SP1_SHIFT 26 #define AIPS_PACRN_TP0_MASK 0x10000000u #define AIPS_PACRN_TP0_SHIFT 28 #define AIPS_PACRN_WP0_MASK 0x20000000u #define AIPS_PACRN_WP0_SHIFT 29 #define AIPS_PACRN_SP0_MASK 0x40000000u #define AIPS_PACRN_SP0_SHIFT 30 /* PACRO Bit Fields */ #define AIPS_PACRO_TP7_MASK 0x1u #define AIPS_PACRO_TP7_SHIFT 0 #define AIPS_PACRO_WP7_MASK 0x2u #define AIPS_PACRO_WP7_SHIFT 1 #define AIPS_PACRO_SP7_MASK 0x4u #define AIPS_PACRO_SP7_SHIFT 2 #define AIPS_PACRO_TP6_MASK 0x10u #define AIPS_PACRO_TP6_SHIFT 4 #define AIPS_PACRO_WP6_MASK 0x20u #define AIPS_PACRO_WP6_SHIFT 5 #define AIPS_PACRO_SP6_MASK 0x40u #define AIPS_PACRO_SP6_SHIFT 6 #define AIPS_PACRO_TP5_MASK 0x100u #define AIPS_PACRO_TP5_SHIFT 8 #define AIPS_PACRO_WP5_MASK 0x200u #define AIPS_PACRO_WP5_SHIFT 9 #define AIPS_PACRO_SP5_MASK 0x400u #define AIPS_PACRO_SP5_SHIFT 10 #define AIPS_PACRO_TP4_MASK 0x1000u #define AIPS_PACRO_TP4_SHIFT 12 #define AIPS_PACRO_WP4_MASK 0x2000u #define AIPS_PACRO_WP4_SHIFT 13 #define AIPS_PACRO_SP4_MASK 0x4000u #define AIPS_PACRO_SP4_SHIFT 14 #define AIPS_PACRO_TP3_MASK 0x10000u #define AIPS_PACRO_TP3_SHIFT 16 #define AIPS_PACRO_WP3_MASK 0x20000u #define AIPS_PACRO_WP3_SHIFT 17 #define AIPS_PACRO_SP3_MASK 0x40000u #define AIPS_PACRO_SP3_SHIFT 18 #define AIPS_PACRO_TP2_MASK 0x100000u #define AIPS_PACRO_TP2_SHIFT 20 #define AIPS_PACRO_WP2_MASK 0x200000u #define AIPS_PACRO_WP2_SHIFT 21 #define AIPS_PACRO_SP2_MASK 0x400000u #define AIPS_PACRO_SP2_SHIFT 22 #define AIPS_PACRO_TP1_MASK 0x1000000u #define AIPS_PACRO_TP1_SHIFT 24 #define AIPS_PACRO_WP1_MASK 0x2000000u #define AIPS_PACRO_WP1_SHIFT 25 #define AIPS_PACRO_SP1_MASK 0x4000000u #define AIPS_PACRO_SP1_SHIFT 26 #define AIPS_PACRO_TP0_MASK 0x10000000u #define AIPS_PACRO_TP0_SHIFT 28 #define AIPS_PACRO_WP0_MASK 0x20000000u #define AIPS_PACRO_WP0_SHIFT 29 #define AIPS_PACRO_SP0_MASK 0x40000000u #define AIPS_PACRO_SP0_SHIFT 30 /* PACRP Bit Fields */ #define AIPS_PACRP_TP7_MASK 0x1u #define AIPS_PACRP_TP7_SHIFT 0 #define AIPS_PACRP_WP7_MASK 0x2u #define AIPS_PACRP_WP7_SHIFT 1 #define AIPS_PACRP_SP7_MASK 0x4u #define AIPS_PACRP_SP7_SHIFT 2 #define AIPS_PACRP_TP6_MASK 0x10u #define AIPS_PACRP_TP6_SHIFT 4 #define AIPS_PACRP_WP6_MASK 0x20u #define AIPS_PACRP_WP6_SHIFT 5 #define AIPS_PACRP_SP6_MASK 0x40u #define AIPS_PACRP_SP6_SHIFT 6 #define AIPS_PACRP_TP5_MASK 0x100u #define AIPS_PACRP_TP5_SHIFT 8 #define AIPS_PACRP_WP5_MASK 0x200u #define AIPS_PACRP_WP5_SHIFT 9 #define AIPS_PACRP_SP5_MASK 0x400u #define AIPS_PACRP_SP5_SHIFT 10 #define AIPS_PACRP_TP4_MASK 0x1000u #define AIPS_PACRP_TP4_SHIFT 12 #define AIPS_PACRP_WP4_MASK 0x2000u #define AIPS_PACRP_WP4_SHIFT 13 #define AIPS_PACRP_SP4_MASK 0x4000u #define AIPS_PACRP_SP4_SHIFT 14 #define AIPS_PACRP_TP3_MASK 0x10000u #define AIPS_PACRP_TP3_SHIFT 16 #define AIPS_PACRP_WP3_MASK 0x20000u #define AIPS_PACRP_WP3_SHIFT 17 #define AIPS_PACRP_SP3_MASK 0x40000u #define AIPS_PACRP_SP3_SHIFT 18 #define AIPS_PACRP_TP2_MASK 0x100000u #define AIPS_PACRP_TP2_SHIFT 20 #define AIPS_PACRP_WP2_MASK 0x200000u #define AIPS_PACRP_WP2_SHIFT 21 #define AIPS_PACRP_SP2_MASK 0x400000u #define AIPS_PACRP_SP2_SHIFT 22 #define AIPS_PACRP_TP1_MASK 0x1000000u #define AIPS_PACRP_TP1_SHIFT 24 #define AIPS_PACRP_WP1_MASK 0x2000000u #define AIPS_PACRP_WP1_SHIFT 25 #define AIPS_PACRP_SP1_MASK 0x4000000u #define AIPS_PACRP_SP1_SHIFT 26 #define AIPS_PACRP_TP0_MASK 0x10000000u #define AIPS_PACRP_TP0_SHIFT 28 #define AIPS_PACRP_WP0_MASK 0x20000000u #define AIPS_PACRP_WP0_SHIFT 29 #define AIPS_PACRP_SP0_MASK 0x40000000u #define AIPS_PACRP_SP0_SHIFT 30 /** * @} */ /* end of group AIPS_Register_Masks */ /* AIPS - Peripheral instance base addresses */ /** Peripheral AIPS0 base pointer */ #define AIPS0_BASE_PTR ((AIPS_MemMapPtr)0x40000000u) /** Peripheral AIPS1 base pointer */ #define AIPS1_BASE_PTR ((AIPS_MemMapPtr)0x40080000u) /* ---------------------------------------------------------------------------- -- AIPS - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros * @{ */ /* AIPS - Register instance definitions */ /* AIPS0 */ #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0_BASE_PTR) #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0_BASE_PTR) #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0_BASE_PTR) #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0_BASE_PTR) #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0_BASE_PTR) #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0_BASE_PTR) #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0_BASE_PTR) #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0_BASE_PTR) #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0_BASE_PTR) #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0_BASE_PTR) #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0_BASE_PTR) #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0_BASE_PTR) #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0_BASE_PTR) #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0_BASE_PTR) #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0_BASE_PTR) #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0_BASE_PTR) #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0_BASE_PTR) /* AIPS1 */ #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1_BASE_PTR) #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1_BASE_PTR) #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1_BASE_PTR) #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1_BASE_PTR) #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1_BASE_PTR) #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1_BASE_PTR) #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1_BASE_PTR) #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1_BASE_PTR) #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1_BASE_PTR) #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1_BASE_PTR) #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1_BASE_PTR) #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1_BASE_PTR) #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1_BASE_PTR) #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1_BASE_PTR) #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1_BASE_PTR) #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1_BASE_PTR) #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1_BASE_PTR) /** * @} */ /* end of group AIPS_Register_Accessor_Macros */ /** * @} */ /* end of group AIPS_Peripheral */ /* ---------------------------------------------------------------------------- -- AXBS ---------------------------------------------------------------------------- */ /** * @addtogroup AXBS_Peripheral AXBS * @{ */ /** AXBS - Peripheral register structure */ typedef struct AXBS_MemMap { struct { /* offset: 0x0, array step: 0x100 */ uint32 PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ uint8 RESERVED_0[12]; uint32 CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ uint8 RESERVED_1[236]; } SLAVE[5]; uint8 RESERVED_0[768]; uint32 MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ uint8 RESERVED_1[252]; uint32 MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ uint8 RESERVED_2[252]; uint32 MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ uint8 RESERVED_3[508]; uint32 MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ uint8 RESERVED_4[252]; uint32 MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ } volatile *AXBS_MemMapPtr; /* ---------------------------------------------------------------------------- -- AXBS - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros * @{ */ /* AXBS - Register accessors */ #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) /** * @} */ /* end of group AXBS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- AXBS Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup AXBS_Register_Masks AXBS Register Masks * @{ */ /* PRS Bit Fields */ #define AXBS_PRS_M0_MASK 0x7u #define AXBS_PRS_M0_SHIFT 0 #define AXBS_PRS_M0(x) (((uint32)(((uint32)(x))<MCR) #define CAN_CTRL1_REG(base) ((base)->CTRL1) #define CAN_TIMER_REG(base) ((base)->TIMER) #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) #define CAN_RX14MASK_REG(base) ((base)->RX14MASK) #define CAN_RX15MASK_REG(base) ((base)->RX15MASK) #define CAN_ECR_REG(base) ((base)->ECR) #define CAN_ESR1_REG(base) ((base)->ESR1) #define CAN_IMASK2_REG(base) ((base)->IMASK2) #define CAN_IMASK1_REG(base) ((base)->IMASK1) #define CAN_IFLAG2_REG(base) ((base)->IFLAG2) #define CAN_IFLAG1_REG(base) ((base)->IFLAG1) #define CAN_CTRL2_REG(base) ((base)->CTRL2) #define CAN_ESR2_REG(base) ((base)->ESR2) #define CAN_CRCR_REG(base) ((base)->CRCR) #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) #define CAN_RXFIR_REG(base) ((base)->RXFIR) #define CAN_CS_REG(base,index) ((base)->MB[index].CS) #define CAN_ID_REG(base,index) ((base)->MB[index].ID) #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) /** * @} */ /* end of group CAN_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /* MCR Bit Fields */ #define CAN_MCR_MAXMB_MASK 0x7Fu #define CAN_MCR_MAXMB_SHIFT 0 #define CAN_MCR_MAXMB(x) (((uint32)(((uint32)(x))<CR0) #define CMP_CR1_REG(base) ((base)->CR1) #define CMP_FPR_REG(base) ((base)->FPR) #define CMP_SCR_REG(base) ((base)->SCR) #define CMP_DACCR_REG(base) ((base)->DACCR) #define CMP_MUXCR_REG(base) ((base)->MUXCR) /** * @} */ /* end of group CMP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CMP Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup CMP_Register_Masks CMP Register Masks * @{ */ /* CR0 Bit Fields */ #define CMP_CR0_HYSTCTR_MASK 0x3u #define CMP_CR0_HYSTCTR_SHIFT 0 #define CMP_CR0_HYSTCTR(x) (((uint8)(((uint8)(x))<CGH1) #define CMT_CGL1_REG(base) ((base)->CGL1) #define CMT_CGH2_REG(base) ((base)->CGH2) #define CMT_CGL2_REG(base) ((base)->CGL2) #define CMT_OC_REG(base) ((base)->OC) #define CMT_MSC_REG(base) ((base)->MSC) #define CMT_CMD1_REG(base) ((base)->CMD1) #define CMT_CMD2_REG(base) ((base)->CMD2) #define CMT_CMD3_REG(base) ((base)->CMD3) #define CMT_CMD4_REG(base) ((base)->CMD4) #define CMT_PPS_REG(base) ((base)->PPS) #define CMT_DMA_REG(base) ((base)->DMA) /** * @} */ /* end of group CMT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CMT Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup CMT_Register_Masks CMT Register Masks * @{ */ /* CGH1 Bit Fields */ #define CMT_CGH1_PH_MASK 0xFFu #define CMT_CGH1_PH_SHIFT 0 #define CMT_CGH1_PH(x) (((uint8)(((uint8)(x))<ACCESS16BIT.CRCL) #define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH) #define CRC_CRC_REG(base) ((base)->CRC) #define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL) #define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU) #define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL) #define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU) #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) #define CRC_GPOLY_REG(base) ((base)->GPOLY) #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) #define CRC_CTRL_REG(base) ((base)->CTRL) #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) /** * @} */ /* end of group CRC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CRC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup CRC_Register_Masks CRC Register Masks * @{ */ /* CRCL Bit Fields */ #define CRC_CRCL_CRCL_MASK 0xFFFFu #define CRC_CRCL_CRCL_SHIFT 0 #define CRC_CRCL_CRCL(x) (((uint16)(((uint16)(x))<base_DHCSR_Read) #define CoreDebug_base_DHCSR_Write_REG(base) ((base)->base_DHCSR_Write) #define CoreDebug_base_DCRSR_REG(base) ((base)->base_DCRSR) #define CoreDebug_base_DCRDR_REG(base) ((base)->base_DCRDR) #define CoreDebug_base_DEMCR_REG(base) ((base)->base_DEMCR) /** * @} */ /* end of group CoreDebug_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CoreDebug Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup CoreDebug_Register_Masks CoreDebug Register Masks * @{ */ /** * @} */ /* end of group CoreDebug_Register_Masks */ /* CoreDebug - Peripheral instance base addresses */ /** Peripheral CoreDebug base pointer */ #define CoreDebug_BASE_PTR ((CoreDebug_MemMapPtr)0xE000EDF0u) /* ---------------------------------------------------------------------------- -- CoreDebug - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup CoreDebug_Register_Accessor_Macros CoreDebug - Register accessor macros * @{ */ /* CoreDebug - Register instance definitions */ /* CoreDebug */ #define DHCSR_Read CoreDebug_base_DHCSR_Read_REG(CoreDebug_BASE_PTR) #define DHCSR_Write CoreDebug_base_DHCSR_Write_REG(CoreDebug_BASE_PTR) #define DCRSR CoreDebug_base_DCRSR_REG(CoreDebug_BASE_PTR) #define DCRDR CoreDebug_base_DCRDR_REG(CoreDebug_BASE_PTR) #define DEMCR CoreDebug_base_DEMCR_REG(CoreDebug_BASE_PTR) /** * @} */ /* end of group CoreDebug_Register_Accessor_Macros */ /** * @} */ /* end of group CoreDebug_Peripheral */ /* ---------------------------------------------------------------------------- -- DAC ---------------------------------------------------------------------------- */ /** * @addtogroup DAC_Peripheral DAC * @{ */ /** DAC - Peripheral register structure */ typedef struct DAC_MemMap { struct { /* offset: 0x0, array step: 0x2 */ uint8 DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ uint8 DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ } DAT[16]; uint8 SR; /**< DAC Status Register, offset: 0x20 */ uint8 C0; /**< DAC Control Register, offset: 0x21 */ uint8 C1; /**< DAC Control Register 1, offset: 0x22 */ uint8 C2; /**< DAC Control Register 2, offset: 0x23 */ } volatile *DAC_MemMapPtr; /* ---------------------------------------------------------------------------- -- DAC - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros * @{ */ /* DAC - Register accessors */ #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL) #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) #define DAC_SR_REG(base) ((base)->SR) #define DAC_C0_REG(base) ((base)->C0) #define DAC_C1_REG(base) ((base)->C1) #define DAC_C2_REG(base) ((base)->C2) /** * @} */ /* end of group DAC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DAC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup DAC_Register_Masks DAC Register Masks * @{ */ /* DATL Bit Fields */ #define DAC_DATL_DATA_MASK 0xFFu #define DAC_DATL_DATA_SHIFT 0 #define DAC_DATL_DATA(x) (((uint8)(((uint8)(x))<CR) #define DMA_ES_REG(base) ((base)->ES) #define DMA_ERQ_REG(base) ((base)->ERQ) #define DMA_EEI_REG(base) ((base)->EEI) #define DMA_CEEI_REG(base) ((base)->CEEI) #define DMA_SEEI_REG(base) ((base)->SEEI) #define DMA_CERQ_REG(base) ((base)->CERQ) #define DMA_SERQ_REG(base) ((base)->SERQ) #define DMA_CDNE_REG(base) ((base)->CDNE) #define DMA_SSRT_REG(base) ((base)->SSRT) #define DMA_CERR_REG(base) ((base)->CERR) #define DMA_CINT_REG(base) ((base)->CINT) #define DMA_INT_REG(base) ((base)->INT) #define DMA_ERR_REG(base) ((base)->ERR) #define DMA_HRS_REG(base) ((base)->HRS) #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) /** * @} */ /* end of group DMA_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /* CR Bit Fields */ #define DMA_CR_EDBG_MASK 0x2u #define DMA_CR_EDBG_SHIFT 1 #define DMA_CR_ERCA_MASK 0x4u #define DMA_CR_ERCA_SHIFT 2 #define DMA_CR_HOE_MASK 0x10u #define DMA_CR_HOE_SHIFT 4 #define DMA_CR_HALT_MASK 0x20u #define DMA_CR_HALT_SHIFT 5 #define DMA_CR_CLM_MASK 0x40u #define DMA_CR_CLM_SHIFT 6 #define DMA_CR_EMLM_MASK 0x80u #define DMA_CR_EMLM_SHIFT 7 #define DMA_CR_ECX_MASK 0x10000u #define DMA_CR_ECX_SHIFT 16 #define DMA_CR_CX_MASK 0x20000u #define DMA_CR_CX_SHIFT 17 /* ES Bit Fields */ #define DMA_ES_DBE_MASK 0x1u #define DMA_ES_DBE_SHIFT 0 #define DMA_ES_SBE_MASK 0x2u #define DMA_ES_SBE_SHIFT 1 #define DMA_ES_SGE_MASK 0x4u #define DMA_ES_SGE_SHIFT 2 #define DMA_ES_NCE_MASK 0x8u #define DMA_ES_NCE_SHIFT 3 #define DMA_ES_DOE_MASK 0x10u #define DMA_ES_DOE_SHIFT 4 #define DMA_ES_DAE_MASK 0x20u #define DMA_ES_DAE_SHIFT 5 #define DMA_ES_SOE_MASK 0x40u #define DMA_ES_SOE_SHIFT 6 #define DMA_ES_SAE_MASK 0x80u #define DMA_ES_SAE_SHIFT 7 #define DMA_ES_ERRCHN_MASK 0xF00u #define DMA_ES_ERRCHN_SHIFT 8 #define DMA_ES_ERRCHN(x) (((uint32)(((uint32)(x))<CHCFG[index]) /** * @} */ /* end of group DMAMUX_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks * @{ */ /* CHCFG Bit Fields */ #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu #define DMAMUX_CHCFG_SOURCE_SHIFT 0 #define DMAMUX_CHCFG_SOURCE(x) (((uint8)(((uint8)(x))<CTRL) #define DWT_CYCCNT_REG(base) ((base)->CYCCNT) #define DWT_CPICNT_REG(base) ((base)->CPICNT) #define DWT_EXCCNT_REG(base) ((base)->EXCCNT) #define DWT_SLEEPCNT_REG(base) ((base)->SLEEPCNT) #define DWT_LSUCNT_REG(base) ((base)->LSUCNT) #define DWT_FOLDCNT_REG(base) ((base)->FOLDCNT) #define DWT_PCSR_REG(base) ((base)->PCSR) #define DWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP) #define DWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK) #define DWT_FUNCTION_REG(base,index) ((base)->COMPARATOR[index].FUNCTION) #define DWT_PID4_REG(base) ((base)->PID4) #define DWT_PID5_REG(base) ((base)->PID5) #define DWT_PID6_REG(base) ((base)->PID6) #define DWT_PID7_REG(base) ((base)->PID7) #define DWT_PID0_REG(base) ((base)->PID0) #define DWT_PID1_REG(base) ((base)->PID1) #define DWT_PID2_REG(base) ((base)->PID2) #define DWT_PID3_REG(base) ((base)->PID3) #define DWT_CID0_REG(base) ((base)->CID0) #define DWT_CID1_REG(base) ((base)->CID1) #define DWT_CID2_REG(base) ((base)->CID2) #define DWT_CID3_REG(base) ((base)->CID3) /** * @} */ /* end of group DWT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DWT Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup DWT_Register_Masks DWT Register Masks * @{ */ /** * @} */ /* end of group DWT_Register_Masks */ /* DWT - Peripheral instance base addresses */ /** Peripheral DWT base pointer */ #define DWT_BASE_PTR ((DWT_MemMapPtr)0xE0001000u) /* ---------------------------------------------------------------------------- -- DWT - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup DWT_Register_Accessor_Macros DWT - Register accessor macros * @{ */ /* DWT - Register instance definitions */ /* DWT */ #define DWT_CTRL DWT_CTRL_REG(DWT_BASE_PTR) #define DWT_CYCCNT DWT_CYCCNT_REG(DWT_BASE_PTR) #define DWT_CPICNT DWT_CPICNT_REG(DWT_BASE_PTR) #define DWT_EXCCNT DWT_EXCCNT_REG(DWT_BASE_PTR) #define DWT_SLEEPCNT DWT_SLEEPCNT_REG(DWT_BASE_PTR) #define DWT_LSUCNT DWT_LSUCNT_REG(DWT_BASE_PTR) #define DWT_FOLDCNT DWT_FOLDCNT_REG(DWT_BASE_PTR) #define DWT_PCSR DWT_PCSR_REG(DWT_BASE_PTR) #define DWT_COMP0 DWT_COMP_REG(DWT_BASE_PTR,0) #define DWT_MASK0 DWT_MASK_REG(DWT_BASE_PTR,0) #define DWT_FUNCTION0 DWT_FUNCTION_REG(DWT_BASE_PTR,0) #define DWT_COMP1 DWT_COMP_REG(DWT_BASE_PTR,1) #define DWT_MASK1 DWT_MASK_REG(DWT_BASE_PTR,1) #define DWT_FUNCTION1 DWT_FUNCTION_REG(DWT_BASE_PTR,1) #define DWT_COMP2 DWT_COMP_REG(DWT_BASE_PTR,2) #define DWT_MASK2 DWT_MASK_REG(DWT_BASE_PTR,2) #define DWT_FUNCTION2 DWT_FUNCTION_REG(DWT_BASE_PTR,2) #define DWT_COMP3 DWT_COMP_REG(DWT_BASE_PTR,3) #define DWT_MASK3 DWT_MASK_REG(DWT_BASE_PTR,3) #define DWT_FUNCTION3 DWT_FUNCTION_REG(DWT_BASE_PTR,3) #define DWT_PID4 DWT_PID4_REG(DWT_BASE_PTR) #define DWT_PID5 DWT_PID5_REG(DWT_BASE_PTR) #define DWT_PID6 DWT_PID6_REG(DWT_BASE_PTR) #define DWT_PID7 DWT_PID7_REG(DWT_BASE_PTR) #define DWT_PID0 DWT_PID0_REG(DWT_BASE_PTR) #define DWT_PID1 DWT_PID1_REG(DWT_BASE_PTR) #define DWT_PID2 DWT_PID2_REG(DWT_BASE_PTR) #define DWT_PID3 DWT_PID3_REG(DWT_BASE_PTR) #define DWT_CID0 DWT_CID0_REG(DWT_BASE_PTR) #define DWT_CID1 DWT_CID1_REG(DWT_BASE_PTR) #define DWT_CID2 DWT_CID2_REG(DWT_BASE_PTR) #define DWT_CID3 DWT_CID3_REG(DWT_BASE_PTR) /* DWT - Register array accessors */ #define DWT_COMP(index) DWT_COMP_REG(DWT_BASE_PTR,index) #define DWT_MASK(index) DWT_MASK_REG(DWT_BASE_PTR,index) #define DWT_FUNCTION(index) DWT_FUNCTION_REG(DWT_BASE_PTR,index) /** * @} */ /* end of group DWT_Register_Accessor_Macros */ /** * @} */ /* end of group DWT_Peripheral */ /* ---------------------------------------------------------------------------- -- ETB ---------------------------------------------------------------------------- */ /** * @addtogroup ETB_Peripheral ETB * @{ */ /** ETB - Peripheral register structure */ typedef struct ETB_MemMap { uint8 RESERVED_0[4]; uint32 RDP; /**< RAM Depth Register, offset: 0x4 */ uint8 RESERVED_1[4]; uint32 STS; /**< Status Register, offset: 0xC */ uint32 RRD; /**< RAM Read Data Register, offset: 0x10 */ uint32 RRP; /**< RAM Read Pointer Register, offset: 0x14 */ uint32 RWP; /**< RAM Write Pointer Register, offset: 0x18 */ uint32 TRG; /**< Trigger Counter Register, offset: 0x1C */ uint32 CTL; /**< Control Register, offset: 0x20 */ uint32 RWD; /**< RAM Write Data Register, offset: 0x24 */ uint8 RESERVED_2[728]; uint32 FFSR; /**< Formatter and Flush Status Register, offset: 0x300 */ uint32 FFCR; /**< Formatter and Flush Control Register, offset: 0x304 */ uint8 RESERVED_3[3032]; uint32 ITMISCOP0; /**< Integration Register, ITMISCOP0, offset: 0xEE0 */ uint32 ITTRFLINACK; /**< Integration Register, ITTRFLINACK, offset: 0xEE4 */ uint32 ITTRFLIN; /**< Integration Register, ITTRFLIN, offset: 0xEE8 */ uint32 ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */ uint32 ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */ uint32 ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */ uint32 ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */ uint8 RESERVED_4[4]; uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ uint8 RESERVED_5[156]; uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ uint8 RESERVED_6[8]; uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ uint8 RESERVED_7[12]; uint32 DEVID; /**< Device ID Register, offset: 0xFC8 */ uint32 DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */ uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ } volatile *ETB_MemMapPtr; /* ---------------------------------------------------------------------------- -- ETB - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros * @{ */ /* ETB - Register accessors */ #define ETB_RDP_REG(base) ((base)->RDP) #define ETB_STS_REG(base) ((base)->STS) #define ETB_RRD_REG(base) ((base)->RRD) #define ETB_RRP_REG(base) ((base)->RRP) #define ETB_RWP_REG(base) ((base)->RWP) #define ETB_TRG_REG(base) ((base)->TRG) #define ETB_CTL_REG(base) ((base)->CTL) #define ETB_RWD_REG(base) ((base)->RWD) #define ETB_FFSR_REG(base) ((base)->FFSR) #define ETB_FFCR_REG(base) ((base)->FFCR) #define ETB_ITMISCOP0_REG(base) ((base)->ITMISCOP0) #define ETB_ITTRFLINACK_REG(base) ((base)->ITTRFLINACK) #define ETB_ITTRFLIN_REG(base) ((base)->ITTRFLIN) #define ETB_ITATBDATA0_REG(base) ((base)->ITATBDATA0) #define ETB_ITATBCTR2_REG(base) ((base)->ITATBCTR2) #define ETB_ITATBCTR1_REG(base) ((base)->ITATBCTR1) #define ETB_ITATBCTR0_REG(base) ((base)->ITATBCTR0) #define ETB_ITCTRL_REG(base) ((base)->ITCTRL) #define ETB_CLAIMSET_REG(base) ((base)->CLAIMSET) #define ETB_CLAIMCLR_REG(base) ((base)->CLAIMCLR) #define ETB_LAR_REG(base) ((base)->LAR) #define ETB_LSR_REG(base) ((base)->LSR) #define ETB_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) #define ETB_DEVID_REG(base) ((base)->DEVID) #define ETB_DEVTYPE_REG(base) ((base)->DEVTYPE) #define ETB_PIDR4_REG(base) ((base)->PIDR4) #define ETB_PIDR5_REG(base) ((base)->PIDR5) #define ETB_PIDR6_REG(base) ((base)->PIDR6) #define ETB_PIDR7_REG(base) ((base)->PIDR7) #define ETB_PIDR0_REG(base) ((base)->PIDR0) #define ETB_PIDR1_REG(base) ((base)->PIDR1) #define ETB_PIDR2_REG(base) ((base)->PIDR2) #define ETB_PIDR3_REG(base) ((base)->PIDR3) #define ETB_CIDR0_REG(base) ((base)->CIDR0) #define ETB_CIDR1_REG(base) ((base)->CIDR1) #define ETB_CIDR2_REG(base) ((base)->CIDR2) #define ETB_CIDR3_REG(base) ((base)->CIDR3) /** * @} */ /* end of group ETB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ETB Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup ETB_Register_Masks ETB Register Masks * @{ */ /** * @} */ /* end of group ETB_Register_Masks */ /* ETB - Peripheral instance base addresses */ /** Peripheral ETB base pointer */ #define ETB_BASE_PTR ((ETB_MemMapPtr)0xE0042000u) /* ---------------------------------------------------------------------------- -- ETB - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup ETB_Register_Accessor_Macros ETB - Register accessor macros * @{ */ /* ETB - Register instance definitions */ /* ETB */ #define ETB_RDP ETB_RDP_REG(ETB_BASE_PTR) #define ETB_STS ETB_STS_REG(ETB_BASE_PTR) #define ETB_RRD ETB_RRD_REG(ETB_BASE_PTR) #define ETB_RRP ETB_RRP_REG(ETB_BASE_PTR) #define ETB_RWP ETB_RWP_REG(ETB_BASE_PTR) #define ETB_TRG ETB_TRG_REG(ETB_BASE_PTR) #define ETB_CTL ETB_CTL_REG(ETB_BASE_PTR) #define ETB_RWD ETB_RWD_REG(ETB_BASE_PTR) #define ETB_FFSR ETB_FFSR_REG(ETB_BASE_PTR) #define ETB_FFCR ETB_FFCR_REG(ETB_BASE_PTR) #define ETB_ITMISCOP0 ETB_ITMISCOP0_REG(ETB_BASE_PTR) #define ETB_ITTRFLINACK ETB_ITTRFLINACK_REG(ETB_BASE_PTR) #define ETB_ITTRFLIN ETB_ITTRFLIN_REG(ETB_BASE_PTR) #define ETB_ITATBDATA0 ETB_ITATBDATA0_REG(ETB_BASE_PTR) #define ETB_ITATBCTR2 ETB_ITATBCTR2_REG(ETB_BASE_PTR) #define ETB_ITATBCTR1 ETB_ITATBCTR1_REG(ETB_BASE_PTR) #define ETB_ITATBCTR0 ETB_ITATBCTR0_REG(ETB_BASE_PTR) #define ETB_ITCTRL ETB_ITCTRL_REG(ETB_BASE_PTR) #define ETB_CLAIMSET ETB_CLAIMSET_REG(ETB_BASE_PTR) #define ETB_CLAIMCLR ETB_CLAIMCLR_REG(ETB_BASE_PTR) #define ETB_LAR ETB_LAR_REG(ETB_BASE_PTR) #define ETB_LSR ETB_LSR_REG(ETB_BASE_PTR) #define ETB_AUTHSTATUS ETB_AUTHSTATUS_REG(ETB_BASE_PTR) #define ETB_DEVID ETB_DEVID_REG(ETB_BASE_PTR) #define ETB_DEVTYPE ETB_DEVTYPE_REG(ETB_BASE_PTR) #define ETB_PIDR4 ETB_PIDR4_REG(ETB_BASE_PTR) #define ETB_PIDR5 ETB_PIDR5_REG(ETB_BASE_PTR) #define ETB_PIDR6 ETB_PIDR6_REG(ETB_BASE_PTR) #define ETB_PIDR7 ETB_PIDR7_REG(ETB_BASE_PTR) #define ETB_PIDR0 ETB_PIDR0_REG(ETB_BASE_PTR) #define ETB_PIDR1 ETB_PIDR1_REG(ETB_BASE_PTR) #define ETB_PIDR2 ETB_PIDR2_REG(ETB_BASE_PTR) #define ETB_PIDR3 ETB_PIDR3_REG(ETB_BASE_PTR) #define ETB_CIDR0 ETB_CIDR0_REG(ETB_BASE_PTR) #define ETB_CIDR1 ETB_CIDR1_REG(ETB_BASE_PTR) #define ETB_CIDR2 ETB_CIDR2_REG(ETB_BASE_PTR) #define ETB_CIDR3 ETB_CIDR3_REG(ETB_BASE_PTR) /** * @} */ /* end of group ETB_Register_Accessor_Macros */ /** * @} */ /* end of group ETB_Peripheral */ /* ---------------------------------------------------------------------------- -- ETF ---------------------------------------------------------------------------- */ /** * @addtogroup ETF_Peripheral ETF * @{ */ /** ETF - Peripheral register structure */ typedef struct ETF_MemMap { uint32 FCR; /**< Funnel Control Register, offset: 0x0 */ uint32 PCR; /**< Priority Control Register, offset: 0x4 */ uint8 RESERVED_0[3812]; uint32 ITATBDATA0; /**< Integration Register, ITATBDATA0, offset: 0xEEC */ uint32 ITATBCTR2; /**< Integration Register, ITATBCTR2, offset: 0xEF0 */ uint32 ITATBCTR1; /**< Integration Register, ITATBCTR1, offset: 0xEF4 */ uint32 ITATBCTR0; /**< Integration Register, ITATBCTR0, offset: 0xEF8 */ uint8 RESERVED_1[4]; uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ uint8 RESERVED_2[156]; uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ uint8 RESERVED_3[8]; uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ uint8 RESERVED_4[12]; uint32 DEVID; /**< Device ID Register, offset: 0xFC8 */ uint32 DEVTYPE; /**< Device Type Identifier Register, offset: 0xFCC */ uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ } volatile *ETF_MemMapPtr; /* ---------------------------------------------------------------------------- -- ETF - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros * @{ */ /* ETF - Register accessors */ #define ETF_FCR_REG(base) ((base)->FCR) #define ETF_PCR_REG(base) ((base)->PCR) #define ETF_ITATBDATA0_REG(base) ((base)->ITATBDATA0) #define ETF_ITATBCTR2_REG(base) ((base)->ITATBCTR2) #define ETF_ITATBCTR1_REG(base) ((base)->ITATBCTR1) #define ETF_ITATBCTR0_REG(base) ((base)->ITATBCTR0) #define ETF_ITCTRL_REG(base) ((base)->ITCTRL) #define ETF_CLAIMSET_REG(base) ((base)->CLAIMSET) #define ETF_CLAIMCLR_REG(base) ((base)->CLAIMCLR) #define ETF_LAR_REG(base) ((base)->LAR) #define ETF_LSR_REG(base) ((base)->LSR) #define ETF_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) #define ETF_DEVID_REG(base) ((base)->DEVID) #define ETF_DEVTYPE_REG(base) ((base)->DEVTYPE) #define ETF_PIDR4_REG(base) ((base)->PIDR4) #define ETF_PIDR5_REG(base) ((base)->PIDR5) #define ETF_PIDR6_REG(base) ((base)->PIDR6) #define ETF_PIDR7_REG(base) ((base)->PIDR7) #define ETF_PIDR0_REG(base) ((base)->PIDR0) #define ETF_PIDR1_REG(base) ((base)->PIDR1) #define ETF_PIDR2_REG(base) ((base)->PIDR2) #define ETF_PIDR3_REG(base) ((base)->PIDR3) #define ETF_CIDR0_REG(base) ((base)->CIDR0) #define ETF_CIDR1_REG(base) ((base)->CIDR1) #define ETF_CIDR2_REG(base) ((base)->CIDR2) #define ETF_CIDR3_REG(base) ((base)->CIDR3) /** * @} */ /* end of group ETF_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ETF Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup ETF_Register_Masks ETF Register Masks * @{ */ /** * @} */ /* end of group ETF_Register_Masks */ /* ETF - Peripheral instance base addresses */ /** Peripheral ETF base pointer */ #define ETF_BASE_PTR ((ETF_MemMapPtr)0xE0043000u) /* ---------------------------------------------------------------------------- -- ETF - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup ETF_Register_Accessor_Macros ETF - Register accessor macros * @{ */ /* ETF - Register instance definitions */ /* ETF */ #define ETF_FCR ETF_FCR_REG(ETF_BASE_PTR) #define ETF_PCR ETF_PCR_REG(ETF_BASE_PTR) #define ETF_ITATBDATA0 ETF_ITATBDATA0_REG(ETF_BASE_PTR) #define ETF_ITATBCTR2 ETF_ITATBCTR2_REG(ETF_BASE_PTR) #define ETF_ITATBCTR1 ETF_ITATBCTR1_REG(ETF_BASE_PTR) #define ETF_ITATBCTR0 ETF_ITATBCTR0_REG(ETF_BASE_PTR) #define ETF_ITCTRL ETF_ITCTRL_REG(ETF_BASE_PTR) #define ETF_CLAIMSET ETF_CLAIMSET_REG(ETF_BASE_PTR) #define ETF_CLAIMCLR ETF_CLAIMCLR_REG(ETF_BASE_PTR) #define ETF_LAR ETF_LAR_REG(ETF_BASE_PTR) #define ETF_LSR ETF_LSR_REG(ETF_BASE_PTR) #define ETF_AUTHSTATUS ETF_AUTHSTATUS_REG(ETF_BASE_PTR) #define ETF_DEVID ETF_DEVID_REG(ETF_BASE_PTR) #define ETF_DEVTYPE ETF_DEVTYPE_REG(ETF_BASE_PTR) #define ETF_PIDR4 ETF_PIDR4_REG(ETF_BASE_PTR) #define ETF_PIDR5 ETF_PIDR5_REG(ETF_BASE_PTR) #define ETF_PIDR6 ETF_PIDR6_REG(ETF_BASE_PTR) #define ETF_PIDR7 ETF_PIDR7_REG(ETF_BASE_PTR) #define ETF_PIDR0 ETF_PIDR0_REG(ETF_BASE_PTR) #define ETF_PIDR1 ETF_PIDR1_REG(ETF_BASE_PTR) #define ETF_PIDR2 ETF_PIDR2_REG(ETF_BASE_PTR) #define ETF_PIDR3 ETF_PIDR3_REG(ETF_BASE_PTR) #define ETF_CIDR0 ETF_CIDR0_REG(ETF_BASE_PTR) #define ETF_CIDR1 ETF_CIDR1_REG(ETF_BASE_PTR) #define ETF_CIDR2 ETF_CIDR2_REG(ETF_BASE_PTR) #define ETF_CIDR3 ETF_CIDR3_REG(ETF_BASE_PTR) /** * @} */ /* end of group ETF_Register_Accessor_Macros */ /** * @} */ /* end of group ETF_Peripheral */ /* ---------------------------------------------------------------------------- -- ETM ---------------------------------------------------------------------------- */ /** * @addtogroup ETM_Peripheral ETM * @{ */ /** ETM - Peripheral register structure */ typedef struct ETM_MemMap { uint32 CR; /**< Main Control Register, offset: 0x0 */ uint32 CCR; /**< Configuration Code Register, offset: 0x4 */ uint32 TRIGGER; /**< Trigger Event Register, offset: 0x8 */ uint8 RESERVED_0[4]; uint32 SR; /**< ETM Status Register, offset: 0x10 */ uint32 SCR; /**< System Configuration Register, offset: 0x14 */ uint8 RESERVED_1[8]; uint32 EEVR; /**< Trace Enable Event Register, offset: 0x20 */ uint32 TECR1; /**< Trace Enable Control 1 Register, offset: 0x24 */ uint32 FFLR; /**< FIFOFULL Level Register, offset: 0x28 */ uint8 RESERVED_2[276]; uint32 CNTRLDVR1; /**< Free-running counter reload value, offset: 0x140 */ uint8 RESERVED_3[156]; uint32 SYNCFR; /**< Synchronization Frequency Register, offset: 0x1E0 */ uint32 IDR; /**< ID Register, offset: 0x1E4 */ uint32 CCER; /**< Configuration Code Extension Register, offset: 0x1E8 */ uint8 RESERVED_4[4]; uint32 TESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register, offset: 0x1F0 */ uint8 RESERVED_5[4]; uint32 TSEVR; /**< Timestamp Event Register, offset: 0x1F8 */ uint8 RESERVED_6[4]; uint32 TRACEIDR; /**< CoreSight Trace ID Register, offset: 0x200 */ uint8 RESERVED_7[4]; uint32 IDR2; /**< ETM ID Register 2, offset: 0x208 */ uint8 RESERVED_8[264]; uint32 PDSR; /**< Device Power-Down Status Register, offset: 0x314 */ uint8 RESERVED_9[3016]; uint32 ITMISCIN; /**< Integration Test Miscelaneous Inputs Register, offset: 0xEE0 */ uint8 RESERVED_10[4]; uint32 ITTRIGOUT; /**< Integration Test Trigger Out Register, offset: 0xEE8 */ uint8 RESERVED_11[4]; uint32 ITATBCTR2; /**< ETM Integration Test ATB Control 2 Register, offset: 0xEF0 */ uint8 RESERVED_12[4]; uint32 ITATBCTR0; /**< ETM Integration Test ATB Control 0 Register, offset: 0xEF8 */ uint8 RESERVED_13[4]; uint32 ITCTRL; /**< Integration Mode Control Register, offset: 0xF00 */ uint8 RESERVED_14[156]; uint32 CLAIMSET; /**< Claim Tag Set Register, offset: 0xFA0 */ uint32 CLAIMCLR; /**< Claim Tag Clear Register, offset: 0xFA4 */ uint8 RESERVED_15[8]; uint32 LAR; /**< Lock Access Register, offset: 0xFB0 */ uint32 LSR; /**< Lock Status Register, offset: 0xFB4 */ uint32 AUTHSTATUS; /**< Authentication Status Register, offset: 0xFB8 */ uint8 RESERVED_16[16]; uint32 DEVTYPE; /**< CoreSight Device Type Register, offset: 0xFCC */ uint32 PIDR4; /**< Peripheral Identification Register 4, offset: 0xFD0 */ uint32 PIDR5; /**< Peripheral Identification Register 5, offset: 0xFD4 */ uint32 PIDR6; /**< Peripheral Identification Register 6, offset: 0xFD8 */ uint32 PIDR7; /**< Peripheral Identification Register 7, offset: 0xFDC */ uint32 PIDR0; /**< Peripheral Identification Register 0, offset: 0xFE0 */ uint32 PIDR1; /**< Peripheral Identification Register 1, offset: 0xFE4 */ uint32 PIDR2; /**< Peripheral Identification Register 2, offset: 0xFE8 */ uint32 PIDR3; /**< Peripheral Identification Register 3, offset: 0xFEC */ uint32 CIDR0; /**< Component Identification Register 0, offset: 0xFF0 */ uint32 CIDR1; /**< Component Identification Register 1, offset: 0xFF4 */ uint32 CIDR2; /**< Component Identification Register 2, offset: 0xFF8 */ uint32 CIDR3; /**< Component Identification Register 3, offset: 0xFFC */ } volatile *ETM_MemMapPtr; /* ---------------------------------------------------------------------------- -- ETM - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros * @{ */ /* ETM - Register accessors */ #define ETM_CR_REG(base) ((base)->CR) #define ETM_CCR_REG(base) ((base)->CCR) #define ETM_TRIGGER_REG(base) ((base)->TRIGGER) #define ETM_SR_REG(base) ((base)->SR) #define ETM_SCR_REG(base) ((base)->SCR) #define ETM_EEVR_REG(base) ((base)->EEVR) #define ETM_TECR1_REG(base) ((base)->TECR1) #define ETM_FFLR_REG(base) ((base)->FFLR) #define ETM_CNTRLDVR1_REG(base) ((base)->CNTRLDVR1) #define ETM_SYNCFR_REG(base) ((base)->SYNCFR) #define ETM_IDR_REG(base) ((base)->IDR) #define ETM_CCER_REG(base) ((base)->CCER) #define ETM_TESSEICR_REG(base) ((base)->TESSEICR) #define ETM_TSEVR_REG(base) ((base)->TSEVR) #define ETM_TRACEIDR_REG(base) ((base)->TRACEIDR) #define ETM_IDR2_REG(base) ((base)->IDR2) #define ETM_PDSR_REG(base) ((base)->PDSR) #define ETM_ITMISCIN_REG(base) ((base)->ITMISCIN) #define ETM_ITTRIGOUT_REG(base) ((base)->ITTRIGOUT) #define ETM_ITATBCTR2_REG(base) ((base)->ITATBCTR2) #define ETM_ITATBCTR0_REG(base) ((base)->ITATBCTR0) #define ETM_ITCTRL_REG(base) ((base)->ITCTRL) #define ETM_CLAIMSET_REG(base) ((base)->CLAIMSET) #define ETM_CLAIMCLR_REG(base) ((base)->CLAIMCLR) #define ETM_LAR_REG(base) ((base)->LAR) #define ETM_LSR_REG(base) ((base)->LSR) #define ETM_AUTHSTATUS_REG(base) ((base)->AUTHSTATUS) #define ETM_DEVTYPE_REG(base) ((base)->DEVTYPE) #define ETM_PIDR4_REG(base) ((base)->PIDR4) #define ETM_PIDR5_REG(base) ((base)->PIDR5) #define ETM_PIDR6_REG(base) ((base)->PIDR6) #define ETM_PIDR7_REG(base) ((base)->PIDR7) #define ETM_PIDR0_REG(base) ((base)->PIDR0) #define ETM_PIDR1_REG(base) ((base)->PIDR1) #define ETM_PIDR2_REG(base) ((base)->PIDR2) #define ETM_PIDR3_REG(base) ((base)->PIDR3) #define ETM_CIDR0_REG(base) ((base)->CIDR0) #define ETM_CIDR1_REG(base) ((base)->CIDR1) #define ETM_CIDR2_REG(base) ((base)->CIDR2) #define ETM_CIDR3_REG(base) ((base)->CIDR3) /** * @} */ /* end of group ETM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ETM Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup ETM_Register_Masks ETM Register Masks * @{ */ /** * @} */ /* end of group ETM_Register_Masks */ /* ETM - Peripheral instance base addresses */ /** Peripheral ETM base pointer */ #define ETM_BASE_PTR ((ETM_MemMapPtr)0xE0041000u) /* ---------------------------------------------------------------------------- -- ETM - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup ETM_Register_Accessor_Macros ETM - Register accessor macros * @{ */ /* ETM - Register instance definitions */ /* ETM */ #define ETMCR ETM_CR_REG(ETM_BASE_PTR) #define ETMCCR ETM_CCR_REG(ETM_BASE_PTR) #define ETMTRIGGER ETM_TRIGGER_REG(ETM_BASE_PTR) #define ETMSR ETM_SR_REG(ETM_BASE_PTR) #define ETMSCR ETM_SCR_REG(ETM_BASE_PTR) #define ETMEEVR ETM_EEVR_REG(ETM_BASE_PTR) #define ETMTECR1 ETM_TECR1_REG(ETM_BASE_PTR) #define ETMFFLR ETM_FFLR_REG(ETM_BASE_PTR) #define ETMCNTRLDVR1 ETM_CNTRLDVR1_REG(ETM_BASE_PTR) #define ETMSYNCFR ETM_SYNCFR_REG(ETM_BASE_PTR) #define ETMIDR ETM_IDR_REG(ETM_BASE_PTR) #define ETMCCER ETM_CCER_REG(ETM_BASE_PTR) #define ETMTESSEICR ETM_TESSEICR_REG(ETM_BASE_PTR) #define ETMTSEVR ETM_TSEVR_REG(ETM_BASE_PTR) #define ETMTRACEIDR ETM_TRACEIDR_REG(ETM_BASE_PTR) #define ETMIDR2 ETM_IDR2_REG(ETM_BASE_PTR) #define ETMPDSR ETM_PDSR_REG(ETM_BASE_PTR) #define ETM_ITMISCIN ETM_ITMISCIN_REG(ETM_BASE_PTR) #define ETM_ITTRIGOUT ETM_ITTRIGOUT_REG(ETM_BASE_PTR) #define ETM_ITATBCTR2 ETM_ITATBCTR2_REG(ETM_BASE_PTR) #define ETM_ITATBCTR0 ETM_ITATBCTR0_REG(ETM_BASE_PTR) #define ETMITCTRL ETM_ITCTRL_REG(ETM_BASE_PTR) #define ETMCLAIMSET ETM_CLAIMSET_REG(ETM_BASE_PTR) #define ETMCLAIMCLR ETM_CLAIMCLR_REG(ETM_BASE_PTR) #define ETMLAR ETM_LAR_REG(ETM_BASE_PTR) #define ETMLSR ETM_LSR_REG(ETM_BASE_PTR) #define ETMAUTHSTATUS ETM_AUTHSTATUS_REG(ETM_BASE_PTR) #define ETMDEVTYPE ETM_DEVTYPE_REG(ETM_BASE_PTR) #define ETMPIDR4 ETM_PIDR4_REG(ETM_BASE_PTR) #define ETMPIDR5 ETM_PIDR5_REG(ETM_BASE_PTR) #define ETMPIDR6 ETM_PIDR6_REG(ETM_BASE_PTR) #define ETMPIDR7 ETM_PIDR7_REG(ETM_BASE_PTR) #define ETMPIDR0 ETM_PIDR0_REG(ETM_BASE_PTR) #define ETMPIDR1 ETM_PIDR1_REG(ETM_BASE_PTR) #define ETMPIDR2 ETM_PIDR2_REG(ETM_BASE_PTR) #define ETMPIDR3 ETM_PIDR3_REG(ETM_BASE_PTR) #define ETMCIDR0 ETM_CIDR0_REG(ETM_BASE_PTR) #define ETMCIDR1 ETM_CIDR1_REG(ETM_BASE_PTR) #define ETMCIDR2 ETM_CIDR2_REG(ETM_BASE_PTR) #define ETMCIDR3 ETM_CIDR3_REG(ETM_BASE_PTR) /** * @} */ /* end of group ETM_Register_Accessor_Macros */ /** * @} */ /* end of group ETM_Peripheral */ /* ---------------------------------------------------------------------------- -- EWM ---------------------------------------------------------------------------- */ /** * @addtogroup EWM_Peripheral EWM * @{ */ /** EWM - Peripheral register structure */ typedef struct EWM_MemMap { uint8 CTRL; /**< Control Register, offset: 0x0 */ uint8 SERV; /**< Service Register, offset: 0x1 */ uint8 CMPL; /**< Compare Low Register, offset: 0x2 */ uint8 CMPH; /**< Compare High Register, offset: 0x3 */ } volatile *EWM_MemMapPtr; /* ---------------------------------------------------------------------------- -- EWM - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros * @{ */ /* EWM - Register accessors */ #define EWM_CTRL_REG(base) ((base)->CTRL) #define EWM_SERV_REG(base) ((base)->SERV) #define EWM_CMPL_REG(base) ((base)->CMPL) #define EWM_CMPH_REG(base) ((base)->CMPH) /** * @} */ /* end of group EWM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- EWM Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup EWM_Register_Masks EWM Register Masks * @{ */ /* CTRL Bit Fields */ #define EWM_CTRL_EWMEN_MASK 0x1u #define EWM_CTRL_EWMEN_SHIFT 0 #define EWM_CTRL_ASSIN_MASK 0x2u #define EWM_CTRL_ASSIN_SHIFT 1 #define EWM_CTRL_INEN_MASK 0x4u #define EWM_CTRL_INEN_SHIFT 2 #define EWM_CTRL_INTEN_MASK 0x8u #define EWM_CTRL_INTEN_SHIFT 3 /* SERV Bit Fields */ #define EWM_SERV_SERVICE_MASK 0xFFu #define EWM_SERV_SERVICE_SHIFT 0 #define EWM_SERV_SERVICE(x) (((uint8)(((uint8)(x))<CS[index].CSAR) #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) #define FB_CSPMCR_REG(base) ((base)->CSPMCR) /** * @} */ /* end of group FB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FB Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup FB_Register_Masks FB Register Masks * @{ */ /* CSAR Bit Fields */ #define FB_CSAR_BA_MASK 0xFFFF0000u #define FB_CSAR_BA_SHIFT 16 #define FB_CSAR_BA(x) (((uint32)(((uint32)(x))<PFAPR) #define FMC_PFB0CR_REG(base) ((base)->PFB0CR) #define FMC_PFB1CR_REG(base) ((base)->PFB1CR) #define FMC_TAGVD_REG(base,index,index2) ((base)->TAGVD[index][index2]) #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) /** * @} */ /* end of group FMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FMC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup FMC_Register_Masks FMC Register Masks * @{ */ /* PFAPR Bit Fields */ #define FMC_PFAPR_M0AP_MASK 0x3u #define FMC_PFAPR_M0AP_SHIFT 0 #define FMC_PFAPR_M0AP(x) (((uint32)(((uint32)(x))<CTRL) #define FPB_REMAP_REG(base) ((base)->REMAP) #define FPB_COMP_REG(base,index) ((base)->COMP[index]) #define FPB_PID4_REG(base) ((base)->PID4) #define FPB_PID5_REG(base) ((base)->PID5) #define FPB_PID6_REG(base) ((base)->PID6) #define FPB_PID7_REG(base) ((base)->PID7) #define FPB_PID0_REG(base) ((base)->PID0) #define FPB_PID1_REG(base) ((base)->PID1) #define FPB_PID2_REG(base) ((base)->PID2) #define FPB_PID3_REG(base) ((base)->PID3) #define FPB_CID0_REG(base) ((base)->CID0) #define FPB_CID1_REG(base) ((base)->CID1) #define FPB_CID2_REG(base) ((base)->CID2) #define FPB_CID3_REG(base) ((base)->CID3) /** * @} */ /* end of group FPB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FPB Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup FPB_Register_Masks FPB Register Masks * @{ */ /** * @} */ /* end of group FPB_Register_Masks */ /* FPB - Peripheral instance base addresses */ /** Peripheral FPB base pointer */ #define FPB_BASE_PTR ((FPB_MemMapPtr)0xE0002000u) /* ---------------------------------------------------------------------------- -- FPB - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup FPB_Register_Accessor_Macros FPB - Register accessor macros * @{ */ /* FPB - Register instance definitions */ /* FPB */ #define FP_CTRL FPB_CTRL_REG(FPB_BASE_PTR) #define FP_REMAP FPB_REMAP_REG(FPB_BASE_PTR) #define FP_COMP0 FPB_COMP_REG(FPB_BASE_PTR,0) #define FP_COMP1 FPB_COMP_REG(FPB_BASE_PTR,1) #define FP_COMP2 FPB_COMP_REG(FPB_BASE_PTR,2) #define FP_COMP3 FPB_COMP_REG(FPB_BASE_PTR,3) #define FP_COMP4 FPB_COMP_REG(FPB_BASE_PTR,4) #define FP_COMP5 FPB_COMP_REG(FPB_BASE_PTR,5) #define FP_COMP6 FPB_COMP_REG(FPB_BASE_PTR,6) #define FP_COMP7 FPB_COMP_REG(FPB_BASE_PTR,7) #define FP_PID4 FPB_PID4_REG(FPB_BASE_PTR) #define FP_PID5 FPB_PID5_REG(FPB_BASE_PTR) #define FP_PID6 FPB_PID6_REG(FPB_BASE_PTR) #define FP_PID7 FPB_PID7_REG(FPB_BASE_PTR) #define FP_PID0 FPB_PID0_REG(FPB_BASE_PTR) #define FP_PID1 FPB_PID1_REG(FPB_BASE_PTR) #define FP_PID2 FPB_PID2_REG(FPB_BASE_PTR) #define FP_PID3 FPB_PID3_REG(FPB_BASE_PTR) #define FP_CID0 FPB_CID0_REG(FPB_BASE_PTR) #define FP_CID1 FPB_CID1_REG(FPB_BASE_PTR) #define FP_CID2 FPB_CID2_REG(FPB_BASE_PTR) #define FP_CID3 FPB_CID3_REG(FPB_BASE_PTR) /* FPB - Register array accessors */ #define FPB_COMP(index) FPB_COMP_REG(FPB_BASE_PTR,index) /** * @} */ /* end of group FPB_Register_Accessor_Macros */ /** * @} */ /* end of group FPB_Peripheral */ /* ---------------------------------------------------------------------------- -- FTFL ---------------------------------------------------------------------------- */ /** * @addtogroup FTFL_Peripheral FTFL * @{ */ /** FTFL - Peripheral register structure */ typedef struct FTFL_MemMap { uint8 FSTAT; /**< Flash Status Register, offset: 0x0 */ uint8 FCNFG; /**< Flash Configuration Register, offset: 0x1 */ uint8 FSEC; /**< Flash Security Register, offset: 0x2 */ uint8 FOPT; /**< Flash Option Register, offset: 0x3 */ uint8 FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ uint8 FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ uint8 FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ uint8 FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ uint8 FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ uint8 FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ uint8 FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ uint8 FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ uint8 FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ uint8 FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ uint8 FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ uint8 FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ uint8 FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ uint8 FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ uint8 FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ uint8 FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ uint8 RESERVED_0[2]; uint8 FEPROT; /**< EEPROM Protection Register, offset: 0x16 */ uint8 FDPROT; /**< Data Flash Protection Register, offset: 0x17 */ } volatile *FTFL_MemMapPtr; /* ---------------------------------------------------------------------------- -- FTFL - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup FTFL_Register_Accessor_Macros FTFL - Register accessor macros * @{ */ /* FTFL - Register accessors */ #define FTFL_FSTAT_REG(base) ((base)->FSTAT) #define FTFL_FCNFG_REG(base) ((base)->FCNFG) #define FTFL_FSEC_REG(base) ((base)->FSEC) #define FTFL_FOPT_REG(base) ((base)->FOPT) #define FTFL_FCCOB3_REG(base) ((base)->FCCOB3) #define FTFL_FCCOB2_REG(base) ((base)->FCCOB2) #define FTFL_FCCOB1_REG(base) ((base)->FCCOB1) #define FTFL_FCCOB0_REG(base) ((base)->FCCOB0) #define FTFL_FCCOB7_REG(base) ((base)->FCCOB7) #define FTFL_FCCOB6_REG(base) ((base)->FCCOB6) #define FTFL_FCCOB5_REG(base) ((base)->FCCOB5) #define FTFL_FCCOB4_REG(base) ((base)->FCCOB4) #define FTFL_FCCOBB_REG(base) ((base)->FCCOBB) #define FTFL_FCCOBA_REG(base) ((base)->FCCOBA) #define FTFL_FCCOB9_REG(base) ((base)->FCCOB9) #define FTFL_FCCOB8_REG(base) ((base)->FCCOB8) #define FTFL_FPROT3_REG(base) ((base)->FPROT3) #define FTFL_FPROT2_REG(base) ((base)->FPROT2) #define FTFL_FPROT1_REG(base) ((base)->FPROT1) #define FTFL_FPROT0_REG(base) ((base)->FPROT0) #define FTFL_FEPROT_REG(base) ((base)->FEPROT) #define FTFL_FDPROT_REG(base) ((base)->FDPROT) /** * @} */ /* end of group FTFL_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FTFL Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup FTFL_Register_Masks FTFL Register Masks * @{ */ /* FSTAT Bit Fields */ #define FTFL_FSTAT_MGSTAT0_MASK 0x1u #define FTFL_FSTAT_MGSTAT0_SHIFT 0 #define FTFL_FSTAT_FPVIOL_MASK 0x10u #define FTFL_FSTAT_FPVIOL_SHIFT 4 #define FTFL_FSTAT_ACCERR_MASK 0x20u #define FTFL_FSTAT_ACCERR_SHIFT 5 #define FTFL_FSTAT_RDCOLERR_MASK 0x40u #define FTFL_FSTAT_RDCOLERR_SHIFT 6 #define FTFL_FSTAT_CCIF_MASK 0x80u #define FTFL_FSTAT_CCIF_SHIFT 7 /* FCNFG Bit Fields */ #define FTFL_FCNFG_EEERDY_MASK 0x1u #define FTFL_FCNFG_EEERDY_SHIFT 0 #define FTFL_FCNFG_RAMRDY_MASK 0x2u #define FTFL_FCNFG_RAMRDY_SHIFT 1 #define FTFL_FCNFG_PFLSH_MASK 0x4u #define FTFL_FCNFG_PFLSH_SHIFT 2 #define FTFL_FCNFG_SWAP_MASK 0x8u #define FTFL_FCNFG_SWAP_SHIFT 3 #define FTFL_FCNFG_ERSSUSP_MASK 0x10u #define FTFL_FCNFG_ERSSUSP_SHIFT 4 #define FTFL_FCNFG_ERSAREQ_MASK 0x20u #define FTFL_FCNFG_ERSAREQ_SHIFT 5 #define FTFL_FCNFG_RDCOLLIE_MASK 0x40u #define FTFL_FCNFG_RDCOLLIE_SHIFT 6 #define FTFL_FCNFG_CCIE_MASK 0x80u #define FTFL_FCNFG_CCIE_SHIFT 7 /* FSEC Bit Fields */ #define FTFL_FSEC_SEC_MASK 0x3u #define FTFL_FSEC_SEC_SHIFT 0 #define FTFL_FSEC_SEC(x) (((uint8)(((uint8)(x))<SC) #define FTM_CNT_REG(base) ((base)->CNT) #define FTM_MOD_REG(base) ((base)->MOD) #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) #define FTM_CNTIN_REG(base) ((base)->CNTIN) #define FTM_STATUS_REG(base) ((base)->STATUS) #define FTM_MODE_REG(base) ((base)->MODE) #define FTM_SYNC_REG(base) ((base)->SYNC) #define FTM_OUTINIT_REG(base) ((base)->OUTINIT) #define FTM_OUTMASK_REG(base) ((base)->OUTMASK) #define FTM_COMBINE_REG(base) ((base)->COMBINE) #define FTM_DEADTIME_REG(base) ((base)->DEADTIME) #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) #define FTM_POL_REG(base) ((base)->POL) #define FTM_FMS_REG(base) ((base)->FMS) #define FTM_FILTER_REG(base) ((base)->FILTER) #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) #define FTM_QDCTRL_REG(base) ((base)->QDCTRL) #define FTM_CONF_REG(base) ((base)->CONF) #define FTM_FLTPOL_REG(base) ((base)->FLTPOL) #define FTM_SYNCONF_REG(base) ((base)->SYNCONF) #define FTM_INVCTRL_REG(base) ((base)->INVCTRL) #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) /** * @} */ /* end of group FTM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FTM Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup FTM_Register_Masks FTM Register Masks * @{ */ /* SC Bit Fields */ #define FTM_SC_PS_MASK 0x7u #define FTM_SC_PS_SHIFT 0 #define FTM_SC_PS(x) (((uint32)(((uint32)(x))<PDOR) #define GPIO_PSOR_REG(base) ((base)->PSOR) #define GPIO_PCOR_REG(base) ((base)->PCOR) #define GPIO_PTOR_REG(base) ((base)->PTOR) #define GPIO_PDIR_REG(base) ((base)->PDIR) #define GPIO_PDDR_REG(base) ((base)->PDDR) /** * @} */ /* end of group GPIO_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /* PDOR Bit Fields */ #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu #define GPIO_PDOR_PDO_SHIFT 0 #define GPIO_PDOR_PDO(x) (((uint32)(((uint32)(x))<A1) #define I2C_F_REG(base) ((base)->F) #define I2C_C1_REG(base) ((base)->C1) #define I2C_S_REG(base) ((base)->S) #define I2C_D_REG(base) ((base)->D) #define I2C_C2_REG(base) ((base)->C2) #define I2C_FLT_REG(base) ((base)->FLT) #define I2C_RA_REG(base) ((base)->RA) #define I2C_SMB_REG(base) ((base)->SMB) #define I2C_A2_REG(base) ((base)->A2) #define I2C_SLTH_REG(base) ((base)->SLTH) #define I2C_SLTL_REG(base) ((base)->SLTL) /** * @} */ /* end of group I2C_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup I2C_Register_Masks I2C Register Masks * @{ */ /* A1 Bit Fields */ #define I2C_A1_AD_MASK 0xFEu #define I2C_A1_AD_SHIFT 1 #define I2C_A1_AD(x) (((uint8)(((uint8)(x))<TCSR) #define I2S_TCR1_REG(base) ((base)->TCR1) #define I2S_TCR2_REG(base) ((base)->TCR2) #define I2S_TCR3_REG(base) ((base)->TCR3) #define I2S_TCR4_REG(base) ((base)->TCR4) #define I2S_TCR5_REG(base) ((base)->TCR5) #define I2S_TDR_REG(base,index) ((base)->TDR[index]) #define I2S_TFR_REG(base,index) ((base)->TFR[index]) #define I2S_TMR_REG(base) ((base)->TMR) #define I2S_RCSR_REG(base) ((base)->RCSR) #define I2S_RCR1_REG(base) ((base)->RCR1) #define I2S_RCR2_REG(base) ((base)->RCR2) #define I2S_RCR3_REG(base) ((base)->RCR3) #define I2S_RCR4_REG(base) ((base)->RCR4) #define I2S_RCR5_REG(base) ((base)->RCR5) #define I2S_RDR_REG(base,index) ((base)->RDR[index]) #define I2S_RFR_REG(base,index) ((base)->RFR[index]) #define I2S_RMR_REG(base) ((base)->RMR) #define I2S_MCR_REG(base) ((base)->MCR) #define I2S_MDR_REG(base) ((base)->MDR) /** * @} */ /* end of group I2S_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /* TCSR Bit Fields */ #define I2S_TCSR_FRDE_MASK 0x1u #define I2S_TCSR_FRDE_SHIFT 0 #define I2S_TCSR_FWDE_MASK 0x2u #define I2S_TCSR_FWDE_SHIFT 1 #define I2S_TCSR_FRIE_MASK 0x100u #define I2S_TCSR_FRIE_SHIFT 8 #define I2S_TCSR_FWIE_MASK 0x200u #define I2S_TCSR_FWIE_SHIFT 9 #define I2S_TCSR_FEIE_MASK 0x400u #define I2S_TCSR_FEIE_SHIFT 10 #define I2S_TCSR_SEIE_MASK 0x800u #define I2S_TCSR_SEIE_SHIFT 11 #define I2S_TCSR_WSIE_MASK 0x1000u #define I2S_TCSR_WSIE_SHIFT 12 #define I2S_TCSR_FRF_MASK 0x10000u #define I2S_TCSR_FRF_SHIFT 16 #define I2S_TCSR_FWF_MASK 0x20000u #define I2S_TCSR_FWF_SHIFT 17 #define I2S_TCSR_FEF_MASK 0x40000u #define I2S_TCSR_FEF_SHIFT 18 #define I2S_TCSR_SEF_MASK 0x80000u #define I2S_TCSR_SEF_SHIFT 19 #define I2S_TCSR_WSF_MASK 0x100000u #define I2S_TCSR_WSF_SHIFT 20 #define I2S_TCSR_SR_MASK 0x1000000u #define I2S_TCSR_SR_SHIFT 24 #define I2S_TCSR_FR_MASK 0x2000000u #define I2S_TCSR_FR_SHIFT 25 #define I2S_TCSR_BCE_MASK 0x10000000u #define I2S_TCSR_BCE_SHIFT 28 #define I2S_TCSR_DBGE_MASK 0x20000000u #define I2S_TCSR_DBGE_SHIFT 29 #define I2S_TCSR_STOPE_MASK 0x40000000u #define I2S_TCSR_STOPE_SHIFT 30 #define I2S_TCSR_TE_MASK 0x80000000u #define I2S_TCSR_TE_SHIFT 31 /* TCR1 Bit Fields */ #define I2S_TCR1_TFW_MASK 0x7u #define I2S_TCR1_TFW_SHIFT 0 #define I2S_TCR1_TFW(x) (((uint32)(((uint32)(x))<STIM_READ[index2]) #define ITM_STIM_WRITE_REG(base,index2) ((base)->STIM_WRITE[index2]) #define ITM_TER_REG(base) ((base)->TER) #define ITM_TPR_REG(base) ((base)->TPR) #define ITM_TCR_REG(base) ((base)->TCR) #define ITM_LAR_REG(base) ((base)->LAR) #define ITM_LSR_REG(base) ((base)->LSR) #define ITM_PID4_REG(base) ((base)->PID4) #define ITM_PID5_REG(base) ((base)->PID5) #define ITM_PID6_REG(base) ((base)->PID6) #define ITM_PID7_REG(base) ((base)->PID7) #define ITM_PID0_REG(base) ((base)->PID0) #define ITM_PID1_REG(base) ((base)->PID1) #define ITM_PID2_REG(base) ((base)->PID2) #define ITM_PID3_REG(base) ((base)->PID3) #define ITM_CID0_REG(base) ((base)->CID0) #define ITM_CID1_REG(base) ((base)->CID1) #define ITM_CID2_REG(base) ((base)->CID2) #define ITM_CID3_REG(base) ((base)->CID3) /** * @} */ /* end of group ITM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ITM Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup ITM_Register_Masks ITM Register Masks * @{ */ /** * @} */ /* end of group ITM_Register_Masks */ /* ITM - Peripheral instance base addresses */ /** Peripheral ITM base pointer */ #define ITM_BASE_PTR ((ITM_MemMapPtr)0xE0000000u) /* ---------------------------------------------------------------------------- -- ITM - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup ITM_Register_Accessor_Macros ITM - Register accessor macros * @{ */ /* ITM - Register instance definitions */ /* ITM */ #define ITM_STIM0_READ ITM_STIM_READ_REG(ITM_BASE_PTR,0) #define ITM_STIM0_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,0) #define ITM_STIM1_READ ITM_STIM_READ_REG(ITM_BASE_PTR,1) #define ITM_STIM1_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,1) #define ITM_STIM2_READ ITM_STIM_READ_REG(ITM_BASE_PTR,2) #define ITM_STIM2_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,2) #define ITM_STIM3_READ ITM_STIM_READ_REG(ITM_BASE_PTR,3) #define ITM_STIM3_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,3) #define ITM_STIM4_READ ITM_STIM_READ_REG(ITM_BASE_PTR,4) #define ITM_STIM4_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,4) #define ITM_STIM5_READ ITM_STIM_READ_REG(ITM_BASE_PTR,5) #define ITM_STIM5_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,5) #define ITM_STIM6_READ ITM_STIM_READ_REG(ITM_BASE_PTR,6) #define ITM_STIM6_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,6) #define ITM_STIM7_READ ITM_STIM_READ_REG(ITM_BASE_PTR,7) #define ITM_STIM7_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,7) #define ITM_STIM8_READ ITM_STIM_READ_REG(ITM_BASE_PTR,8) #define ITM_STIM8_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,8) #define ITM_STIM9_READ ITM_STIM_READ_REG(ITM_BASE_PTR,9) #define ITM_STIM9_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,9) #define ITM_STIM10_READ ITM_STIM_READ_REG(ITM_BASE_PTR,10) #define ITM_STIM10_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,10) #define ITM_STIM11_READ ITM_STIM_READ_REG(ITM_BASE_PTR,11) #define ITM_STIM11_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,11) #define ITM_STIM12_READ ITM_STIM_READ_REG(ITM_BASE_PTR,12) #define ITM_STIM12_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,12) #define ITM_STIM13_READ ITM_STIM_READ_REG(ITM_BASE_PTR,13) #define ITM_STIM13_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,13) #define ITM_STIM14_READ ITM_STIM_READ_REG(ITM_BASE_PTR,14) #define ITM_STIM14_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,14) #define ITM_STIM15_READ ITM_STIM_READ_REG(ITM_BASE_PTR,15) #define ITM_STIM15_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,15) #define ITM_STIM16_READ ITM_STIM_READ_REG(ITM_BASE_PTR,16) #define ITM_STIM16_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,16) #define ITM_STIM17_READ ITM_STIM_READ_REG(ITM_BASE_PTR,17) #define ITM_STIM17_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,17) #define ITM_STIM18_READ ITM_STIM_READ_REG(ITM_BASE_PTR,18) #define ITM_STIM18_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,18) #define ITM_STIM19_READ ITM_STIM_READ_REG(ITM_BASE_PTR,19) #define ITM_STIM19_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,19) #define ITM_STIM20_READ ITM_STIM_READ_REG(ITM_BASE_PTR,20) #define ITM_STIM20_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,20) #define ITM_STIM21_READ ITM_STIM_READ_REG(ITM_BASE_PTR,21) #define ITM_STIM21_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,21) #define ITM_STIM22_READ ITM_STIM_READ_REG(ITM_BASE_PTR,22) #define ITM_STIM22_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,22) #define ITM_STIM23_READ ITM_STIM_READ_REG(ITM_BASE_PTR,23) #define ITM_STIM23_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,23) #define ITM_STIM24_READ ITM_STIM_READ_REG(ITM_BASE_PTR,24) #define ITM_STIM24_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,24) #define ITM_STIM25_READ ITM_STIM_READ_REG(ITM_BASE_PTR,25) #define ITM_STIM25_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,25) #define ITM_STIM26_READ ITM_STIM_READ_REG(ITM_BASE_PTR,26) #define ITM_STIM26_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,26) #define ITM_STIM27_READ ITM_STIM_READ_REG(ITM_BASE_PTR,27) #define ITM_STIM27_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,27) #define ITM_STIM28_READ ITM_STIM_READ_REG(ITM_BASE_PTR,28) #define ITM_STIM28_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,28) #define ITM_STIM29_READ ITM_STIM_READ_REG(ITM_BASE_PTR,29) #define ITM_STIM29_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,29) #define ITM_STIM30_READ ITM_STIM_READ_REG(ITM_BASE_PTR,30) #define ITM_STIM30_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,30) #define ITM_STIM31_READ ITM_STIM_READ_REG(ITM_BASE_PTR,31) #define ITM_STIM31_WRITE ITM_STIM_WRITE_REG(ITM_BASE_PTR,31) #define ITM_TER ITM_TER_REG(ITM_BASE_PTR) #define ITM_TPR ITM_TPR_REG(ITM_BASE_PTR) #define ITM_TCR ITM_TCR_REG(ITM_BASE_PTR) #define ITM_LAR ITM_LAR_REG(ITM_BASE_PTR) #define ITM_LSR ITM_LSR_REG(ITM_BASE_PTR) #define ITM_PID4 ITM_PID4_REG(ITM_BASE_PTR) #define ITM_PID5 ITM_PID5_REG(ITM_BASE_PTR) #define ITM_PID6 ITM_PID6_REG(ITM_BASE_PTR) #define ITM_PID7 ITM_PID7_REG(ITM_BASE_PTR) #define ITM_PID0 ITM_PID0_REG(ITM_BASE_PTR) #define ITM_PID1 ITM_PID1_REG(ITM_BASE_PTR) #define ITM_PID2 ITM_PID2_REG(ITM_BASE_PTR) #define ITM_PID3 ITM_PID3_REG(ITM_BASE_PTR) #define ITM_CID0 ITM_CID0_REG(ITM_BASE_PTR) #define ITM_CID1 ITM_CID1_REG(ITM_BASE_PTR) #define ITM_CID2 ITM_CID2_REG(ITM_BASE_PTR) #define ITM_CID3 ITM_CID3_REG(ITM_BASE_PTR) /* ITM - Register array accessors */ #define ITM_STIM_READ(index2) ITM_STIM_READ_REG(ITM_BASE_PTR,index2) #define ITM_STIM_WRITE(index2) ITM_STIM_WRITE_REG(ITM_BASE_PTR,index2) /** * @} */ /* end of group ITM_Register_Accessor_Macros */ /** * @} */ /* end of group ITM_Peripheral */ /* ---------------------------------------------------------------------------- -- LLWU ---------------------------------------------------------------------------- */ /** * @addtogroup LLWU_Peripheral LLWU * @{ */ /** LLWU - Peripheral register structure */ typedef struct LLWU_MemMap { uint8 PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */ uint8 PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */ uint8 PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */ uint8 PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */ uint8 ME; /**< LLWU Module Enable Register, offset: 0x4 */ uint8 F1; /**< LLWU Flag 1 Register, offset: 0x5 */ uint8 F2; /**< LLWU Flag 2 Register, offset: 0x6 */ uint8 F3; /**< LLWU Flag 3 Register, offset: 0x7 */ uint8 FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */ uint8 FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */ uint8 RST; /**< LLWU Reset Enable Register, offset: 0xA */ } volatile *LLWU_MemMapPtr; /* ---------------------------------------------------------------------------- -- LLWU - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros * @{ */ /* LLWU - Register accessors */ #define LLWU_PE1_REG(base) ((base)->PE1) #define LLWU_PE2_REG(base) ((base)->PE2) #define LLWU_PE3_REG(base) ((base)->PE3) #define LLWU_PE4_REG(base) ((base)->PE4) #define LLWU_ME_REG(base) ((base)->ME) #define LLWU_F1_REG(base) ((base)->F1) #define LLWU_F2_REG(base) ((base)->F2) #define LLWU_F3_REG(base) ((base)->F3) #define LLWU_FILT1_REG(base) ((base)->FILT1) #define LLWU_FILT2_REG(base) ((base)->FILT2) #define LLWU_RST_REG(base) ((base)->RST) /** * @} */ /* end of group LLWU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LLWU Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup LLWU_Register_Masks LLWU Register Masks * @{ */ /* PE1 Bit Fields */ #define LLWU_PE1_WUPE0_MASK 0x3u #define LLWU_PE1_WUPE0_SHIFT 0 #define LLWU_PE1_WUPE0(x) (((uint8)(((uint8)(x))<CSR) #define LPTMR_PSR_REG(base) ((base)->PSR) #define LPTMR_CMR_REG(base) ((base)->CMR) #define LPTMR_CNR_REG(base) ((base)->CNR) /** * @} */ /* end of group LPTMR_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /* CSR Bit Fields */ #define LPTMR_CSR_TEN_MASK 0x1u #define LPTMR_CSR_TEN_SHIFT 0 #define LPTMR_CSR_TMS_MASK 0x2u #define LPTMR_CSR_TMS_SHIFT 1 #define LPTMR_CSR_TFC_MASK 0x4u #define LPTMR_CSR_TFC_SHIFT 2 #define LPTMR_CSR_TPP_MASK 0x8u #define LPTMR_CSR_TPP_SHIFT 3 #define LPTMR_CSR_TPS_MASK 0x30u #define LPTMR_CSR_TPS_SHIFT 4 #define LPTMR_CSR_TPS(x) (((uint32)(((uint32)(x))<C1) #define MCG_C2_REG(base) ((base)->C2) #define MCG_C3_REG(base) ((base)->C3) #define MCG_C4_REG(base) ((base)->C4) #define MCG_C5_REG(base) ((base)->C5) #define MCG_C6_REG(base) ((base)->C6) #define MCG_S_REG(base) ((base)->S) #define MCG_SC_REG(base) ((base)->SC) #define MCG_ATCVH_REG(base) ((base)->ATCVH) #define MCG_ATCVL_REG(base) ((base)->ATCVL) #define MCG_C7_REG(base) ((base)->C7) #define MCG_C8_REG(base) ((base)->C8) /** * @} */ /* end of group MCG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCG Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup MCG_Register_Masks MCG Register Masks * @{ */ /* C1 Bit Fields */ #define MCG_C1_IREFSTEN_MASK 0x1u #define MCG_C1_IREFSTEN_SHIFT 0 #define MCG_C1_IRCLKEN_MASK 0x2u #define MCG_C1_IRCLKEN_SHIFT 1 #define MCG_C1_IREFS_MASK 0x4u #define MCG_C1_IREFS_SHIFT 2 #define MCG_C1_FRDIV_MASK 0x38u #define MCG_C1_FRDIV_SHIFT 3 #define MCG_C1_FRDIV(x) (((uint8)(((uint8)(x))<PLASC) #define MCM_PLAMC_REG(base) ((base)->PLAMC) #define MCM_CR_REG(base) ((base)->CR) #define MCM_ISR_REG(base) ((base)->ISR) #define MCM_ETBCC_REG(base) ((base)->ETBCC) #define MCM_ETBRL_REG(base) ((base)->ETBRL) #define MCM_ETBCNT_REG(base) ((base)->ETBCNT) #define MCM_PID_REG(base) ((base)->PID) /** * @} */ /* end of group MCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /* PLASC Bit Fields */ #define MCM_PLASC_ASC_MASK 0xFFu #define MCM_PLASC_ASC_SHIFT 0 #define MCM_PLASC_ASC(x) (((uint16)(((uint16)(x))<CESR) #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) /** * @} */ /* end of group MPU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MPU Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup MPU_Register_Masks MPU Register Masks * @{ */ /* CESR Bit Fields */ #define MPU_CESR_VLD_MASK 0x1u #define MPU_CESR_VLD_SHIFT 0 #define MPU_CESR_NRGD_MASK 0xF00u #define MPU_CESR_NRGD_SHIFT 8 #define MPU_CESR_NRGD(x) (((uint32)(((uint32)(x))<BACKKEY3) #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) #define NV_FPROT3_REG(base) ((base)->FPROT3) #define NV_FPROT2_REG(base) ((base)->FPROT2) #define NV_FPROT1_REG(base) ((base)->FPROT1) #define NV_FPROT0_REG(base) ((base)->FPROT0) #define NV_FSEC_REG(base) ((base)->FSEC) #define NV_FOPT_REG(base) ((base)->FOPT) #define NV_FEPROT_REG(base) ((base)->FEPROT) #define NV_FDPROT_REG(base) ((base)->FDPROT) /** * @} */ /* end of group NV_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- NV Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup NV_Register_Masks NV Register Masks * @{ */ /* BACKKEY3 Bit Fields */ #define NV_BACKKEY3_KEY_MASK 0xFFu #define NV_BACKKEY3_KEY_SHIFT 0 #define NV_BACKKEY3_KEY(x) (((uint8)(((uint8)(x))<ISER[index]) #define NVIC_ICER_REG(base,index) ((base)->ICER[index]) #define NVIC_ISPR_REG(base,index) ((base)->ISPR[index]) #define NVIC_ICPR_REG(base,index) ((base)->ICPR[index]) #define NVIC_IABR_REG(base,index) ((base)->IABR[index]) #define NVIC_IP_REG(base,index) ((base)->IP[index]) #define NVIC_STIR_REG(base,index) ((base)->STIR[index]) /** * @} */ /* end of group NVIC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- NVIC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup NVIC_Register_Masks NVIC Register Masks * @{ */ /* ISER Bit Fields */ #define NVIC_ISER_SETENA_MASK 0xFFFFFFFFu #define NVIC_ISER_SETENA_SHIFT 0 #define NVIC_ISER_SETENA(x) (((uint32)(((uint32)(x))<CR) /** * @} */ /* end of group OSC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- OSC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup OSC_Register_Masks OSC Register Masks * @{ */ /* CR Bit Fields */ #define OSC_CR_SC16P_MASK 0x1u #define OSC_CR_SC16P_SHIFT 0 #define OSC_CR_SC8P_MASK 0x2u #define OSC_CR_SC8P_SHIFT 1 #define OSC_CR_SC4P_MASK 0x4u #define OSC_CR_SC4P_SHIFT 2 #define OSC_CR_SC2P_MASK 0x8u #define OSC_CR_SC2P_SHIFT 3 #define OSC_CR_EREFSTEN_MASK 0x20u #define OSC_CR_EREFSTEN_SHIFT 5 #define OSC_CR_ERCLKEN_MASK 0x80u #define OSC_CR_ERCLKEN_SHIFT 7 /** * @} */ /* end of group OSC_Register_Masks */ /* OSC - Peripheral instance base addresses */ /** Peripheral OSC base pointer */ #define OSC_BASE_PTR ((OSC_MemMapPtr)0x40065000u) /* ---------------------------------------------------------------------------- -- OSC - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros * @{ */ /* OSC - Register instance definitions */ /* OSC */ #define OSC_CR OSC_CR_REG(OSC_BASE_PTR) /** * @} */ /* end of group OSC_Register_Accessor_Macros */ /** * @} */ /* end of group OSC_Peripheral */ /* ---------------------------------------------------------------------------- -- PDB ---------------------------------------------------------------------------- */ /** * @addtogroup PDB_Peripheral PDB * @{ */ /** PDB - Peripheral register structure */ typedef struct PDB_MemMap { uint32 SC; /**< Status and Control Register, offset: 0x0 */ uint32 MOD; /**< Modulus Register, offset: 0x4 */ uint32 CNT; /**< Counter Register, offset: 0x8 */ uint32 IDLY; /**< Interrupt Delay Register, offset: 0xC */ struct { /* offset: 0x10, array step: 0x28 */ uint32 C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */ uint32 S; /**< Channel n Status Register, array offset: 0x14, array step: 0x28 */ uint32 DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */ uint8 RESERVED_0[24]; } CH[2]; uint8 RESERVED_0[240]; struct { /* offset: 0x150, array step: 0x8 */ uint32 INTC; /**< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */ uint32 INT; /**< DAC Interval n Register, array offset: 0x154, array step: 0x8 */ } DAC[2]; uint8 RESERVED_1[48]; uint32 POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ uint32 PODLY[3]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ } volatile *PDB_MemMapPtr; /* ---------------------------------------------------------------------------- -- PDB - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros * @{ */ /* PDB - Register accessors */ #define PDB_SC_REG(base) ((base)->SC) #define PDB_MOD_REG(base) ((base)->MOD) #define PDB_CNT_REG(base) ((base)->CNT) #define PDB_IDLY_REG(base) ((base)->IDLY) #define PDB_C1_REG(base,index) ((base)->CH[index].C1) #define PDB_S_REG(base,index) ((base)->CH[index].S) #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) #define PDB_INT_REG(base,index) ((base)->DAC[index].INT) #define PDB_POEN_REG(base) ((base)->POEN) #define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) /** * @} */ /* end of group PDB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PDB Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup PDB_Register_Masks PDB Register Masks * @{ */ /* SC Bit Fields */ #define PDB_SC_LDOK_MASK 0x1u #define PDB_SC_LDOK_SHIFT 0 #define PDB_SC_CONT_MASK 0x2u #define PDB_SC_CONT_SHIFT 1 #define PDB_SC_MULT_MASK 0xCu #define PDB_SC_MULT_SHIFT 2 #define PDB_SC_MULT(x) (((uint32)(((uint32)(x))<MCR) #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) /** * @} */ /* end of group PIT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PIT Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup PIT_Register_Masks PIT Register Masks * @{ */ /* MCR Bit Fields */ #define PIT_MCR_FRZ_MASK 0x1u #define PIT_MCR_FRZ_SHIFT 0 #define PIT_MCR_MDIS_MASK 0x2u #define PIT_MCR_MDIS_SHIFT 1 /* LDVAL Bit Fields */ #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu #define PIT_LDVAL_TSV_SHIFT 0 #define PIT_LDVAL_TSV(x) (((uint32)(((uint32)(x))<LVDSC1) #define PMC_LVDSC2_REG(base) ((base)->LVDSC2) #define PMC_REGSC_REG(base) ((base)->REGSC) /** * @} */ /* end of group PMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PMC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup PMC_Register_Masks PMC Register Masks * @{ */ /* LVDSC1 Bit Fields */ #define PMC_LVDSC1_LVDV_MASK 0x3u #define PMC_LVDSC1_LVDV_SHIFT 0 #define PMC_LVDSC1_LVDV(x) (((uint8)(((uint8)(x))<PCR[index]) #define PORT_GPCLR_REG(base) ((base)->GPCLR) #define PORT_GPCHR_REG(base) ((base)->GPCHR) #define PORT_ISFR_REG(base) ((base)->ISFR) #define PORT_DFER_REG(base) ((base)->DFER) #define PORT_DFCR_REG(base) ((base)->DFCR) #define PORT_DFWR_REG(base) ((base)->DFWR) /** * @} */ /* end of group PORT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /* PCR Bit Fields */ #define PORT_PCR_PS_MASK 0x1u #define PORT_PCR_PS_SHIFT 0 #define PORT_PCR_PE_MASK 0x2u #define PORT_PCR_PE_SHIFT 1 #define PORT_PCR_SRE_MASK 0x4u #define PORT_PCR_SRE_SHIFT 2 #define PORT_PCR_PFE_MASK 0x10u #define PORT_PCR_PFE_SHIFT 4 #define PORT_PCR_ODE_MASK 0x20u #define PORT_PCR_ODE_SHIFT 5 #define PORT_PCR_DSE_MASK 0x40u #define PORT_PCR_DSE_SHIFT 6 #define PORT_PCR_MUX_MASK 0x700u #define PORT_PCR_MUX_SHIFT 8 #define PORT_PCR_MUX(x) (((uint32)(((uint32)(x))<SRS0) #define RCM_SRS1_REG(base) ((base)->SRS1) #define RCM_RPFC_REG(base) ((base)->RPFC) #define RCM_RPFW_REG(base) ((base)->RPFW) #define RCM_MR_REG(base) ((base)->MR) /** * @} */ /* end of group RCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RCM Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup RCM_Register_Masks RCM Register Masks * @{ */ /* SRS0 Bit Fields */ #define RCM_SRS0_WAKEUP_MASK 0x1u #define RCM_SRS0_WAKEUP_SHIFT 0 #define RCM_SRS0_LVD_MASK 0x2u #define RCM_SRS0_LVD_SHIFT 1 #define RCM_SRS0_LOC_MASK 0x4u #define RCM_SRS0_LOC_SHIFT 2 #define RCM_SRS0_LOL_MASK 0x8u #define RCM_SRS0_LOL_SHIFT 3 #define RCM_SRS0_WDOG_MASK 0x20u #define RCM_SRS0_WDOG_SHIFT 5 #define RCM_SRS0_PIN_MASK 0x40u #define RCM_SRS0_PIN_SHIFT 6 #define RCM_SRS0_POR_MASK 0x80u #define RCM_SRS0_POR_SHIFT 7 /* SRS1 Bit Fields */ #define RCM_SRS1_JTAG_MASK 0x1u #define RCM_SRS1_JTAG_SHIFT 0 #define RCM_SRS1_LOCKUP_MASK 0x2u #define RCM_SRS1_LOCKUP_SHIFT 1 #define RCM_SRS1_SW_MASK 0x4u #define RCM_SRS1_SW_SHIFT 2 #define RCM_SRS1_MDM_AP_MASK 0x8u #define RCM_SRS1_MDM_AP_SHIFT 3 #define RCM_SRS1_EZPT_MASK 0x10u #define RCM_SRS1_EZPT_SHIFT 4 #define RCM_SRS1_SACKERR_MASK 0x20u #define RCM_SRS1_SACKERR_SHIFT 5 /* RPFC Bit Fields */ #define RCM_RPFC_RSTFLTSRW_MASK 0x3u #define RCM_RPFC_RSTFLTSRW_SHIFT 0 #define RCM_RPFC_RSTFLTSRW(x) (((uint8)(((uint8)(x))<REG[index]) /** * @} */ /* end of group RFSYS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RFSYS Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup RFSYS_Register_Masks RFSYS Register Masks * @{ */ /* REG Bit Fields */ #define RFSYS_REG_LL_MASK 0xFFu #define RFSYS_REG_LL_SHIFT 0 #define RFSYS_REG_LL(x) (((uint32)(((uint32)(x))<REG[index]) /** * @} */ /* end of group RFVBAT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RFVBAT Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks * @{ */ /* REG Bit Fields */ #define RFVBAT_REG_LL_MASK 0xFFu #define RFVBAT_REG_LL_SHIFT 0 #define RFVBAT_REG_LL(x) (((uint32)(((uint32)(x))<TSR) #define RTC_TPR_REG(base) ((base)->TPR) #define RTC_TAR_REG(base) ((base)->TAR) #define RTC_TCR_REG(base) ((base)->TCR) #define RTC_CR_REG(base) ((base)->CR) #define RTC_SR_REG(base) ((base)->SR) #define RTC_LR_REG(base) ((base)->LR) #define RTC_IER_REG(base) ((base)->IER) #define RTC_WAR_REG(base) ((base)->WAR) #define RTC_RAR_REG(base) ((base)->RAR) /** * @} */ /* end of group RTC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RTC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup RTC_Register_Masks RTC Register Masks * @{ */ /* TSR Bit Fields */ #define RTC_TSR_TSR_MASK 0xFFFFFFFFu #define RTC_TSR_TSR_SHIFT 0 #define RTC_TSR_TSR(x) (((uint32)(((uint32)(x))<ACTLR) #define SCB_CPUID_REG(base) ((base)->CPUID) #define SCB_ICSR_REG(base) ((base)->ICSR) #define SCB_VTOR_REG(base) ((base)->VTOR) #define SCB_AIRCR_REG(base) ((base)->AIRCR) #define SCB_SCR_REG(base) ((base)->SCR) #define SCB_CCR_REG(base) ((base)->CCR) #define SCB_SHPR1_REG(base) ((base)->SHPR1) #define SCB_SHPR2_REG(base) ((base)->SHPR2) #define SCB_SHPR3_REG(base) ((base)->SHPR3) #define SCB_SHCSR_REG(base) ((base)->SHCSR) #define SCB_CFSR_REG(base) ((base)->CFSR) #define SCB_HFSR_REG(base) ((base)->HFSR) #define SCB_DFSR_REG(base) ((base)->DFSR) #define SCB_MMFAR_REG(base) ((base)->MMFAR) #define SCB_BFAR_REG(base) ((base)->BFAR) #define SCB_AFSR_REG(base) ((base)->AFSR) /** * @} */ /* end of group SCB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SCB Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup SCB_Register_Masks SCB Register Masks * @{ */ /* ACTLR Bit Fields */ #define SCB_ACTLR_DISMCYCINT_MASK 0x1u #define SCB_ACTLR_DISMCYCINT_SHIFT 0 #define SCB_ACTLR_DISDEFWBUF_MASK 0x2u #define SCB_ACTLR_DISDEFWBUF_SHIFT 1 #define SCB_ACTLR_DISFOLD_MASK 0x4u #define SCB_ACTLR_DISFOLD_SHIFT 2 /* CPUID Bit Fields */ #define SCB_CPUID_REVISION_MASK 0xFu #define SCB_CPUID_REVISION_SHIFT 0 #define SCB_CPUID_REVISION(x) (((uint32)(((uint32)(x))<DSADDR) #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) #define SDHC_CMDARG_REG(base) ((base)->CMDARG) #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) #define SDHC_DATPORT_REG(base) ((base)->DATPORT) #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) #define SDHC_PROCTL_REG(base) ((base)->PROCTL) #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) #define SDHC_WML_REG(base) ((base)->WML) #define SDHC_FEVT_REG(base) ((base)->FEVT) #define SDHC_ADMAES_REG(base) ((base)->ADMAES) #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) #define SDHC_VENDOR_REG(base) ((base)->VENDOR) #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) /** * @} */ /* end of group SDHC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SDHC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup SDHC_Register_Masks SDHC Register Masks * @{ */ /* DSADDR Bit Fields */ #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu #define SDHC_DSADDR_DSADDR_SHIFT 2 #define SDHC_DSADDR_DSADDR(x) (((uint32)(((uint32)(x))<SOPT1) #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) #define SIM_SOPT2_REG(base) ((base)->SOPT2) #define SIM_SOPT4_REG(base) ((base)->SOPT4) #define SIM_SOPT5_REG(base) ((base)->SOPT5) #define SIM_SOPT7_REG(base) ((base)->SOPT7) #define SIM_SDID_REG(base) ((base)->SDID) #define SIM_SCGC1_REG(base) ((base)->SCGC1) #define SIM_SCGC2_REG(base) ((base)->SCGC2) #define SIM_SCGC3_REG(base) ((base)->SCGC3) #define SIM_SCGC4_REG(base) ((base)->SCGC4) #define SIM_SCGC5_REG(base) ((base)->SCGC5) #define SIM_SCGC6_REG(base) ((base)->SCGC6) #define SIM_SCGC7_REG(base) ((base)->SCGC7) #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) #define SIM_FCFG1_REG(base) ((base)->FCFG1) #define SIM_FCFG2_REG(base) ((base)->FCFG2) #define SIM_UIDH_REG(base) ((base)->UIDH) #define SIM_UIDMH_REG(base) ((base)->UIDMH) #define SIM_UIDML_REG(base) ((base)->UIDML) #define SIM_UIDL_REG(base) ((base)->UIDL) /** * @} */ /* end of group SIM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SIM Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup SIM_Register_Masks SIM Register Masks * @{ */ /* SOPT1 Bit Fields */ #define SIM_SOPT1_RAMSIZE_MASK 0xF000u #define SIM_SOPT1_RAMSIZE_SHIFT 12 #define SIM_SOPT1_RAMSIZE(x) (((uint32)(((uint32)(x))<PMPROT) #define SMC_PMCTRL_REG(base) ((base)->PMCTRL) #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) #define SMC_PMSTAT_REG(base) ((base)->PMSTAT) /** * @} */ /* end of group SMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SMC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup SMC_Register_Masks SMC Register Masks * @{ */ /* PMPROT Bit Fields */ #define SMC_PMPROT_AVLLS_MASK 0x2u #define SMC_PMPROT_AVLLS_SHIFT 1 #define SMC_PMPROT_ALLS_MASK 0x8u #define SMC_PMPROT_ALLS_SHIFT 3 #define SMC_PMPROT_AVLP_MASK 0x20u #define SMC_PMPROT_AVLP_SHIFT 5 /* PMCTRL Bit Fields */ #define SMC_PMCTRL_STOPM_MASK 0x7u #define SMC_PMCTRL_STOPM_SHIFT 0 #define SMC_PMCTRL_STOPM(x) (((uint8)(((uint8)(x))<MCR) #define SPI_TCR_REG(base) ((base)->TCR) #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) #define SPI_SR_REG(base) ((base)->SR) #define SPI_RSER_REG(base) ((base)->RSER) #define SPI_PUSHR_REG(base) ((base)->PUSHR) #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) #define SPI_POPR_REG(base) ((base)->POPR) #define SPI_TXFR0_REG(base) ((base)->TXFR0) #define SPI_TXFR1_REG(base) ((base)->TXFR1) #define SPI_TXFR2_REG(base) ((base)->TXFR2) #define SPI_TXFR3_REG(base) ((base)->TXFR3) #define SPI_RXFR0_REG(base) ((base)->RXFR0) #define SPI_RXFR1_REG(base) ((base)->RXFR1) #define SPI_RXFR2_REG(base) ((base)->RXFR2) #define SPI_RXFR3_REG(base) ((base)->RXFR3) /** * @} */ /* end of group SPI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SPI Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup SPI_Register_Masks SPI Register Masks * @{ */ /* MCR Bit Fields */ #define SPI_MCR_HALT_MASK 0x1u #define SPI_MCR_HALT_SHIFT 0 #define SPI_MCR_SMPL_PT_MASK 0x300u #define SPI_MCR_SMPL_PT_SHIFT 8 #define SPI_MCR_SMPL_PT(x) (((uint32)(((uint32)(x))<CSR) #define SysTick_RVR_REG(base) ((base)->RVR) #define SysTick_CVR_REG(base) ((base)->CVR) #define SysTick_CALIB_REG(base) ((base)->CALIB) /** * @} */ /* end of group SysTick_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SysTick Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup SysTick_Register_Masks SysTick Register Masks * @{ */ /* CSR Bit Fields */ #define SysTick_CSR_ENABLE_MASK 0x1u #define SysTick_CSR_ENABLE_SHIFT 0 #define SysTick_CSR_TICKINT_MASK 0x2u #define SysTick_CSR_TICKINT_SHIFT 1 #define SysTick_CSR_CLKSOURCE_MASK 0x4u #define SysTick_CSR_CLKSOURCE_SHIFT 2 #define SysTick_CSR_COUNTFLAG_MASK 0x10000u #define SysTick_CSR_COUNTFLAG_SHIFT 16 /* RVR Bit Fields */ #define SysTick_RVR_RELOAD_MASK 0xFFFFFFu #define SysTick_RVR_RELOAD_SHIFT 0 #define SysTick_RVR_RELOAD(x) (((uint32)(((uint32)(x))<SSPSR) #define TPIU_CSPSR_REG(base) ((base)->CSPSR) #define TPIU_ACPR_REG(base) ((base)->ACPR) #define TPIU_SPPR_REG(base) ((base)->SPPR) #define TPIU_FFSR_REG(base) ((base)->FFSR) #define TPIU_FFCR_REG(base) ((base)->FFCR) #define TPIU_FSCR_REG(base) ((base)->FSCR) #define TPIU_TRIGGER_REG(base) ((base)->TRIGGER) #define TPIU_FIFODATA0_REG(base) ((base)->FIFODATA0) #define TPIU_ITATBCTR2_REG(base) ((base)->ITATBCTR2) #define TPIU_ITATBCTR0_REG(base) ((base)->ITATBCTR0) #define TPIU_FIFODATA1_REG(base) ((base)->FIFODATA1) #define TPIU_ITCTRL_REG(base) ((base)->ITCTRL) #define TPIU_CLAIMSET_REG(base) ((base)->CLAIMSET) #define TPIU_CLAIMCLR_REG(base) ((base)->CLAIMCLR) #define TPIU_DEVID_REG(base) ((base)->DEVID) #define TPIU_PID4_REG(base) ((base)->PID4) #define TPIU_PID5_REG(base) ((base)->PID5) #define TPIU_PID6_REG(base) ((base)->PID6) #define TPIU_PID7_REG(base) ((base)->PID7) #define TPIU_PID0_REG(base) ((base)->PID0) #define TPIU_PID1_REG(base) ((base)->PID1) #define TPIU_PID2_REG(base) ((base)->PID2) #define TPIU_PID3_REG(base) ((base)->PID3) #define TPIU_CID0_REG(base) ((base)->CID0) #define TPIU_CID1_REG(base) ((base)->CID1) #define TPIU_CID2_REG(base) ((base)->CID2) #define TPIU_CID4_REG(base) ((base)->CID4) /** * @} */ /* end of group TPIU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- TPIU Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup TPIU_Register_Masks TPIU Register Masks * @{ */ /** * @} */ /* end of group TPIU_Register_Masks */ /* TPIU - Peripheral instance base addresses */ /** Peripheral TPIU base pointer */ #define TPIU_BASE_PTR ((TPIU_MemMapPtr)0xE0040000u) /* ---------------------------------------------------------------------------- -- TPIU - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup TPIU_Register_Accessor_Macros TPIU - Register accessor macros * @{ */ /* TPIU - Register instance definitions */ /* TPIU */ #define TPIU_SSPSR TPIU_SSPSR_REG(TPIU_BASE_PTR) #define TPIU_CSPSR TPIU_CSPSR_REG(TPIU_BASE_PTR) #define TPIU_ACPR TPIU_ACPR_REG(TPIU_BASE_PTR) #define TPIU_SPPR TPIU_SPPR_REG(TPIU_BASE_PTR) #define TPIU_FFSR TPIU_FFSR_REG(TPIU_BASE_PTR) #define TPIU_FFCR TPIU_FFCR_REG(TPIU_BASE_PTR) #define TPIU_FSCR TPIU_FSCR_REG(TPIU_BASE_PTR) #define TPIU_TRIGGER TPIU_TRIGGER_REG(TPIU_BASE_PTR) #define TPIU_FIFODATA0 TPIU_FIFODATA0_REG(TPIU_BASE_PTR) #define TPIU_ITATBCTR2 TPIU_ITATBCTR2_REG(TPIU_BASE_PTR) #define TPIU_ITATBCTR0 TPIU_ITATBCTR0_REG(TPIU_BASE_PTR) #define TPIU_FIFODATA1 TPIU_FIFODATA1_REG(TPIU_BASE_PTR) #define TPIU_ITCTRL TPIU_ITCTRL_REG(TPIU_BASE_PTR) #define TPIU_CLAIMSET TPIU_CLAIMSET_REG(TPIU_BASE_PTR) #define TPIU_CLAIMCLR TPIU_CLAIMCLR_REG(TPIU_BASE_PTR) #define TPIU_DEVID TPIU_DEVID_REG(TPIU_BASE_PTR) #define TPIU_PID4 TPIU_PID4_REG(TPIU_BASE_PTR) #define TPIU_PID5 TPIU_PID5_REG(TPIU_BASE_PTR) #define TPIU_PID6 TPIU_PID6_REG(TPIU_BASE_PTR) #define TPIU_PID7 TPIU_PID7_REG(TPIU_BASE_PTR) #define TPIU_PID0 TPIU_PID0_REG(TPIU_BASE_PTR) #define TPIU_PID1 TPIU_PID1_REG(TPIU_BASE_PTR) #define TPIU_PID2 TPIU_PID2_REG(TPIU_BASE_PTR) #define TPIU_PID3 TPIU_PID3_REG(TPIU_BASE_PTR) #define TPIU_CID0 TPIU_CID0_REG(TPIU_BASE_PTR) #define TPIU_CID1 TPIU_CID1_REG(TPIU_BASE_PTR) #define TPIU_CID2 TPIU_CID2_REG(TPIU_BASE_PTR) #define TPIU_CID3 TPIU_CID4_REG(TPIU_BASE_PTR) /** * @} */ /* end of group TPIU_Register_Accessor_Macros */ /** * @} */ /* end of group TPIU_Peripheral */ /* ---------------------------------------------------------------------------- -- TSI ---------------------------------------------------------------------------- */ /** * @addtogroup TSI_Peripheral TSI * @{ */ /** TSI - Peripheral register structure */ typedef struct TSI_MemMap { uint32 GENCS; /**< General Control and Status Register, offset: 0x0 */ uint32 SCANC; /**< SCAN Control Register, offset: 0x4 */ uint32 PEN; /**< Pin Enable Register, offset: 0x8 */ uint32 WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */ uint8 RESERVED_0[240]; uint32 CNTR1; /**< Counter Register, offset: 0x100 */ uint32 CNTR3; /**< Counter Register, offset: 0x104 */ uint32 CNTR5; /**< Counter Register, offset: 0x108 */ uint32 CNTR7; /**< Counter Register, offset: 0x10C */ uint32 CNTR9; /**< Counter Register, offset: 0x110 */ uint32 CNTR11; /**< Counter Register, offset: 0x114 */ uint32 CNTR13; /**< Counter Register, offset: 0x118 */ uint32 CNTR15; /**< Counter Register, offset: 0x11C */ uint32 THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */ } volatile *TSI_MemMapPtr; /* ---------------------------------------------------------------------------- -- TSI - Register accessor macros ---------------------------------------------------------------------------- */ /** * @addtogroup TSI_Register_Accessor_Macros TSI - Register accessor macros * @{ */ /* TSI - Register accessors */ #define TSI_GENCS_REG(base) ((base)->GENCS) #define TSI_SCANC_REG(base) ((base)->SCANC) #define TSI_PEN_REG(base) ((base)->PEN) #define TSI_WUCNTR_REG(base) ((base)->WUCNTR) #define TSI_CNTR1_REG(base) ((base)->CNTR1) #define TSI_CNTR3_REG(base) ((base)->CNTR3) #define TSI_CNTR5_REG(base) ((base)->CNTR5) #define TSI_CNTR7_REG(base) ((base)->CNTR7) #define TSI_CNTR9_REG(base) ((base)->CNTR9) #define TSI_CNTR11_REG(base) ((base)->CNTR11) #define TSI_CNTR13_REG(base) ((base)->CNTR13) #define TSI_CNTR15_REG(base) ((base)->CNTR15) #define TSI_THRESHOLD_REG(base) ((base)->THRESHOLD) /** * @} */ /* end of group TSI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- TSI Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup TSI_Register_Masks TSI Register Masks * @{ */ /* GENCS Bit Fields */ #define TSI_GENCS_STPE_MASK 0x1u #define TSI_GENCS_STPE_SHIFT 0 #define TSI_GENCS_STM_MASK 0x2u #define TSI_GENCS_STM_SHIFT 1 #define TSI_GENCS_ESOR_MASK 0x10u #define TSI_GENCS_ESOR_SHIFT 4 #define TSI_GENCS_ERIE_MASK 0x20u #define TSI_GENCS_ERIE_SHIFT 5 #define TSI_GENCS_TSIIE_MASK 0x40u #define TSI_GENCS_TSIIE_SHIFT 6 #define TSI_GENCS_TSIEN_MASK 0x80u #define TSI_GENCS_TSIEN_SHIFT 7 #define TSI_GENCS_SWTS_MASK 0x100u #define TSI_GENCS_SWTS_SHIFT 8 #define TSI_GENCS_SCNIP_MASK 0x200u #define TSI_GENCS_SCNIP_SHIFT 9 #define TSI_GENCS_OVRF_MASK 0x1000u #define TSI_GENCS_OVRF_SHIFT 12 #define TSI_GENCS_EXTERF_MASK 0x2000u #define TSI_GENCS_EXTERF_SHIFT 13 #define TSI_GENCS_OUTRGF_MASK 0x4000u #define TSI_GENCS_OUTRGF_SHIFT 14 #define TSI_GENCS_EOSF_MASK 0x8000u #define TSI_GENCS_EOSF_SHIFT 15 #define TSI_GENCS_PS_MASK 0x70000u #define TSI_GENCS_PS_SHIFT 16 #define TSI_GENCS_PS(x) (((uint32)(((uint32)(x))<BDH) #define UART_BDL_REG(base) ((base)->BDL) #define UART_C1_REG(base) ((base)->C1) #define UART_C2_REG(base) ((base)->C2) #define UART_S1_REG(base) ((base)->S1) #define UART_S2_REG(base) ((base)->S2) #define UART_C3_REG(base) ((base)->C3) #define UART_D_REG(base) ((base)->D) #define UART_MA1_REG(base) ((base)->MA1) #define UART_MA2_REG(base) ((base)->MA2) #define UART_C4_REG(base) ((base)->C4) #define UART_C5_REG(base) ((base)->C5) #define UART_ED_REG(base) ((base)->ED) #define UART_MODEM_REG(base) ((base)->MODEM) #define UART_IR_REG(base) ((base)->IR) #define UART_PFIFO_REG(base) ((base)->PFIFO) #define UART_CFIFO_REG(base) ((base)->CFIFO) #define UART_SFIFO_REG(base) ((base)->SFIFO) #define UART_TWFIFO_REG(base) ((base)->TWFIFO) #define UART_TCFIFO_REG(base) ((base)->TCFIFO) #define UART_RWFIFO_REG(base) ((base)->RWFIFO) #define UART_RCFIFO_REG(base) ((base)->RCFIFO) #define UART_C7816_REG(base) ((base)->C7816) #define UART_IE7816_REG(base) ((base)->IE7816) #define UART_IS7816_REG(base) ((base)->IS7816) #define UART_WP7816_T_TYPE0_REG(base) ((base)->WP7816_T_TYPE0) #define UART_WP7816_T_TYPE1_REG(base) ((base)->WP7816_T_TYPE1) #define UART_WN7816_REG(base) ((base)->WN7816) #define UART_WF7816_REG(base) ((base)->WF7816) #define UART_ET7816_REG(base) ((base)->ET7816) #define UART_TL7816_REG(base) ((base)->TL7816) /** * @} */ /* end of group UART_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- UART Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup UART_Register_Masks UART Register Masks * @{ */ /* BDH Bit Fields */ #define UART_BDH_SBR_MASK 0x1Fu #define UART_BDH_SBR_SHIFT 0 #define UART_BDH_SBR(x) (((uint8)(((uint8)(x))<PERID) #define USB_IDCOMP_REG(base) ((base)->IDCOMP) #define USB_REV_REG(base) ((base)->REV) #define USB_ADDINFO_REG(base) ((base)->ADDINFO) #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) #define USB_OTGICR_REG(base) ((base)->OTGICR) #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) #define USB_OTGCTL_REG(base) ((base)->OTGCTL) #define USB_ISTAT_REG(base) ((base)->ISTAT) #define USB_INTEN_REG(base) ((base)->INTEN) #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) #define USB_ERREN_REG(base) ((base)->ERREN) #define USB_STAT_REG(base) ((base)->STAT) #define USB_CTL_REG(base) ((base)->CTL) #define USB_ADDR_REG(base) ((base)->ADDR) #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) #define USB_FRMNUML_REG(base) ((base)->FRMNUML) #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) #define USB_TOKEN_REG(base) ((base)->TOKEN) #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) #define USB_USBCTRL_REG(base) ((base)->USBCTRL) #define USB_OBSERVE_REG(base) ((base)->OBSERVE) #define USB_CONTROL_REG(base) ((base)->CONTROL) #define USB_USBTRC0_REG(base) ((base)->USBTRC0) #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) /** * @} */ /* end of group USB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /* PERID Bit Fields */ #define USB_PERID_ID_MASK 0x3Fu #define USB_PERID_ID_SHIFT 0 #define USB_PERID_ID(x) (((uint8)(((uint8)(x))<CONTROL) #define USBDCD_CLOCK_REG(base) ((base)->CLOCK) #define USBDCD_STATUS_REG(base) ((base)->STATUS) #define USBDCD_TIMER0_REG(base) ((base)->TIMER0) #define USBDCD_TIMER1_REG(base) ((base)->TIMER1) #define USBDCD_TIMER2_REG(base) ((base)->TIMER2) /** * @} */ /* end of group USBDCD_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USBDCD Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup USBDCD_Register_Masks USBDCD Register Masks * @{ */ /* CONTROL Bit Fields */ #define USBDCD_CONTROL_IACK_MASK 0x1u #define USBDCD_CONTROL_IACK_SHIFT 0 #define USBDCD_CONTROL_IF_MASK 0x100u #define USBDCD_CONTROL_IF_SHIFT 8 #define USBDCD_CONTROL_IE_MASK 0x10000u #define USBDCD_CONTROL_IE_SHIFT 16 #define USBDCD_CONTROL_START_MASK 0x1000000u #define USBDCD_CONTROL_START_SHIFT 24 #define USBDCD_CONTROL_SR_MASK 0x2000000u #define USBDCD_CONTROL_SR_SHIFT 25 /* CLOCK Bit Fields */ #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32)(((uint32)(x))<TRM) #define VREF_SC_REG(base) ((base)->SC) /** * @} */ /* end of group VREF_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- VREF Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup VREF_Register_Masks VREF Register Masks * @{ */ /* TRM Bit Fields */ #define VREF_TRM_TRIM_MASK 0x3Fu #define VREF_TRM_TRIM_SHIFT 0 #define VREF_TRM_TRIM(x) (((uint8)(((uint8)(x))<STCTRLH) #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) #define WDOG_TOVALH_REG(base) ((base)->TOVALH) #define WDOG_TOVALL_REG(base) ((base)->TOVALL) #define WDOG_WINH_REG(base) ((base)->WINH) #define WDOG_WINL_REG(base) ((base)->WINL) #define WDOG_REFRESH_REG(base) ((base)->REFRESH) #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) #define WDOG_PRESC_REG(base) ((base)->PRESC) /** * @} */ /* end of group WDOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /* STCTRLH Bit Fields */ #define WDOG_STCTRLH_WDOGEN_MASK 0x1u #define WDOG_STCTRLH_WDOGEN_SHIFT 0 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u #define WDOG_STCTRLH_CLKSRC_SHIFT 1 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 #define WDOG_STCTRLH_WINEN_MASK 0x8u #define WDOG_STCTRLH_WINEN_SHIFT 3 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 #define WDOG_STCTRLH_DBGEN_MASK 0x20u #define WDOG_STCTRLH_DBGEN_SHIFT 5 #define WDOG_STCTRLH_STOPEN_MASK 0x40u #define WDOG_STCTRLH_STOPEN_SHIFT 6 #define WDOG_STCTRLH_WAITEN_MASK 0x80u #define WDOG_STCTRLH_WAITEN_SHIFT 7 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u #define WDOG_STCTRLH_TESTWDOG_SHIFT 10 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u #define WDOG_STCTRLH_TESTSEL_SHIFT 11 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u #define WDOG_STCTRLH_BYTESEL_SHIFT 12 #define WDOG_STCTRLH_BYTESEL(x) (((uint16)(((uint16)(x))<