296 lines
11 KiB
C
296 lines
11 KiB
C
/* ###################################################################
|
|
** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
|
|
** Filename : Cpu.c
|
|
** Project : FS_TC_Test
|
|
** Processor : MK20DN512VLL10
|
|
** Component : MK20DN512LL10
|
|
** Version : Component 01.000, Driver 01.04, CPU db: 3.00.000
|
|
** Datasheet : K20P144M100SF2V2RM Rev. 2, Jun 2012
|
|
** Compiler : GNU C Compiler
|
|
** Date/Time : 2014-12-22, 13:39, # CodeGen: 7
|
|
** Abstract :
|
|
**
|
|
** Settings :
|
|
**
|
|
** Contents :
|
|
** No public methods
|
|
**
|
|
** Copyright : 1997 - 2014 Freescale Semiconductor, Inc.
|
|
** All Rights Reserved.
|
|
**
|
|
** Redistribution and use in source and binary forms, with or without modification,
|
|
** are permitted provided that the following conditions are met:
|
|
**
|
|
** o Redistributions of source code must retain the above copyright notice, this list
|
|
** of conditions and the following disclaimer.
|
|
**
|
|
** o Redistributions in binary form must reproduce the above copyright notice, this
|
|
** list of conditions and the following disclaimer in the documentation and/or
|
|
** other materials provided with the distribution.
|
|
**
|
|
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
|
** contributors may be used to endorse or promote products derived from this
|
|
** software without specific prior written permission.
|
|
**
|
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
|
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
**
|
|
** http: www.freescale.com
|
|
** mail: support@freescale.com
|
|
** ###################################################################*/
|
|
/*!
|
|
** @file Cpu.c
|
|
** @version 01.04
|
|
** @brief
|
|
**
|
|
*/
|
|
/*!
|
|
** @addtogroup Cpu_module Cpu module documentation
|
|
** @{
|
|
*/
|
|
|
|
/* MODULE Cpu. */
|
|
|
|
/* {Default RTOS Adapter} No RTOS includes */
|
|
|
|
#include "hal/derivative.h"
|
|
#include "Cpu.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/* Global variables */
|
|
volatile uint8 SR_reg; /* Current value of the FAULTMASK register */
|
|
volatile uint8 SR_lock = 0x00U; /* Lock */
|
|
|
|
void LowLevelInit(void);
|
|
void InitClocks(void);
|
|
|
|
|
|
CpuTypeDef Cpu =
|
|
{
|
|
.initClocks = InitClocks,
|
|
.initLowLevel = LowLevelInit,
|
|
};
|
|
|
|
/*
|
|
** ===================================================================
|
|
** Method : Cpu_SetBASEPRI (component MK20DN512LL10)
|
|
**
|
|
** Description :
|
|
** This method sets the BASEPRI core register.
|
|
** This method is internal. It is used by Processor Expert only.
|
|
** ===================================================================
|
|
*/
|
|
void Cpu_SetBASEPRI(uint32 Level);
|
|
|
|
/*
|
|
** ===================================================================
|
|
** Method : Cpu_INT_NMIInterrupt (component MK20DN512LL10)
|
|
**
|
|
** Description :
|
|
** This ISR services the Non Maskable Interrupt interrupt.
|
|
** This method is internal. It is used by Processor Expert only.
|
|
** ===================================================================
|
|
*/
|
|
|
|
void __attribute__ ((interrupt)) Cpu_INT_NMIInterrupt(void)
|
|
{
|
|
|
|
}
|
|
|
|
/*
|
|
** ===================================================================
|
|
** Method : Cpu_Cpu_Interrupt (component MK20DN512LL10)
|
|
**
|
|
** Description :
|
|
** This ISR services an unused interrupt/exception vector.
|
|
** This method is internal. It is used by Processor Expert only.
|
|
** ===================================================================
|
|
*/
|
|
void __attribute__ ((interrupt)) Cpu_Interrupt(void)
|
|
{
|
|
/* This code can be changed using the CPU component property "Build Options / Unhandled int code" */
|
|
PE_DEBUGHALT();
|
|
}
|
|
|
|
|
|
/***************************************************************//**
|
|
\fn InitClocks(void)
|
|
\brief Initialize the clock PLL
|
|
|
|
This function inializes the PLL to 96MHz (with 16MHz crystal
|
|
freqeuncy) and then switches to PLL clock.
|
|
So the following frequencies are used:
|
|
Core: 96MHz
|
|
Bus: 48MHz
|
|
FlexBus: 48MHz
|
|
Flash: 24MHz
|
|
|
|
This routine has been generated by ProcessorExpert and cleaned
|
|
up manually.
|
|
********************************************************************/
|
|
void InitClocks(void)
|
|
{
|
|
//Turn on clocking for all ports to enable pin routing
|
|
SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK
|
|
| SIM_SCGC5_PORTB_MASK
|
|
| SIM_SCGC5_PORTC_MASK
|
|
| SIM_SCGC5_PORTD_MASK
|
|
| SIM_SCGC5_PORTE_MASK );
|
|
|
|
//PLL already selected by bootloader? => exit
|
|
if((MCG_S & 0x0C)==0x0C) return;
|
|
|
|
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
|
|
SIM_CLKDIV1_OUTDIV2(0x01) |
|
|
SIM_CLKDIV1_OUTDIV3(0x03) |
|
|
SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
|
|
|
|
if((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U)
|
|
{
|
|
/* PMC_REGSC: ACKISO=1 */
|
|
PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
|
|
}
|
|
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
|
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
|
|
SIM_CLKDIV1_OUTDIV2(0x01) |
|
|
SIM_CLKDIV1_OUTDIV3(0x01) |
|
|
SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */
|
|
/* SIM_SOPT2: PLLFLLSEL=1 */
|
|
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK|SIM_SOPT2_CLKOUTSEL(6); /* Select PLL as a clock source for various peripherals */
|
|
/* SIM_SOPT1: OSC32KSEL=3 */
|
|
SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
|
|
/* Switch to FBE Mode */
|
|
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
|
|
MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);
|
|
/* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
|
OSC_CR = OSC_CR_ERCLKEN_MASK;
|
|
/* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
|
MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK);
|
|
/* MCG_C4: DMX32=0,DRST_DRS=0 */
|
|
MCG_C4 &= (uint8)~(uint8)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
|
|
/* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
|
|
MCG_C5 = MCG_C5_PRDIV0(0x03);
|
|
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
|
MCG_C6 = MCG_C6_VDIV0(0x00);
|
|
while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U); /* Check that the oscillator is running */
|
|
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U); /* Check that the source of the FLL reference clock is the external reference clock. */
|
|
while((MCG_S & 0x0CU) != 0x08U); /* Wait until external reference clock is selected as MCG output */
|
|
/* Switch to PBE Mode */
|
|
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
|
|
MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00));
|
|
while((MCG_S & 0x0CU) != 0x08U); /* Wait until external reference clock is selected as MCG output */
|
|
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
|
|
/* Switch to PEE Mode */
|
|
/* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
|
MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK);
|
|
while((MCG_S & 0x0CU) != 0x0CU); /* Wait until output of the PLL is selected */
|
|
}
|
|
|
|
/*
|
|
** ===================================================================
|
|
** Method : Cpu_SetBASEPRI (component MK20DN512LL10)
|
|
**
|
|
** Description :
|
|
** This method sets the BASEPRI core register.
|
|
** This method is internal. It is used by Processor Expert only.
|
|
** ===================================================================
|
|
*/
|
|
/*lint -save -e586 -e950 Disable MISRA rule (2.1,1.1) checking. */
|
|
#ifdef _lint
|
|
#define Cpu_SetBASEPRI(Level) /* empty */
|
|
#else
|
|
void Cpu_SetBASEPRI(uint32 Level) {
|
|
__asm ("msr basepri, %[input]"::[input] "r" (Level):);
|
|
}
|
|
#endif
|
|
/*lint -restore Enable MISRA rule (2.1,1.1) checking. */
|
|
|
|
|
|
|
|
/***************************************************************//**
|
|
\fn LowLevelInit(void)
|
|
\brief Low level initialization of the MCU
|
|
|
|
This function does some low level initialization of the MCU.
|
|
Generated by ProcessorExpert and then cleaned up manually.
|
|
********************************************************************/
|
|
void LowLevelInit(void)
|
|
{
|
|
/* Initialization of the RCM module */ //***TEST_OK: Kann je nach Beschaltung des Reset-Pins zum Absturz führen
|
|
/* RCM_RPFW: RSTFLTSEL=0 */
|
|
RCM_RPFW &= (uint8)~(uint8)(RCM_RPFW_RSTFLTSEL(0x1F));
|
|
/* RCM_RPFC: RSTFLTSS=0,RSTFLTSRW=0 */
|
|
RCM_RPFC &= (uint8)~(uint8)(
|
|
RCM_RPFC_RSTFLTSS_MASK |
|
|
RCM_RPFC_RSTFLTSRW(0x03)
|
|
);
|
|
/* Initialization of the FTFL_FlashConfig module */
|
|
/* SIM_SCGC7: MPU=1 */
|
|
SIM_SCGC7 |= SIM_SCGC7_MPU_MASK;
|
|
/* Initialization of the MPU module */
|
|
|
|
//Turn off MPU (important e.g. for the USB stack to work properly)
|
|
/* MPU_CESR: SPERR=0,VLD=0 */
|
|
MPU_CESR &= (uint32)~(uint32)((MPU_CESR_SPERR(0x1F) | MPU_CESR_VLD_MASK));
|
|
|
|
/* Initialization of the PMC module */
|
|
/* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */
|
|
PMC_LVDSC1 = (uint8)((PMC_LVDSC1 & (uint8)~(uint8)(
|
|
PMC_LVDSC1_LVDIE_MASK |
|
|
PMC_LVDSC1_LVDV(0x03)
|
|
)) | (uint8)(
|
|
PMC_LVDSC1_LVDACK_MASK |
|
|
PMC_LVDSC1_LVDRE_MASK
|
|
));
|
|
/* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */
|
|
PMC_LVDSC2 = (uint8)((PMC_LVDSC2 & (uint8)~(uint8)(
|
|
PMC_LVDSC2_LVWIE_MASK |
|
|
PMC_LVDSC2_LVWV(0x03)
|
|
)) | (uint8)(
|
|
PMC_LVDSC2_LVWACK_MASK
|
|
));
|
|
/* PMC_REGSC: BGEN=0,ACKISO=0,BGBE=0 */
|
|
PMC_REGSC &= (uint8)~(uint8)(
|
|
PMC_REGSC_BGEN_MASK |
|
|
PMC_REGSC_ACKISO_MASK |
|
|
PMC_REGSC_BGBE_MASK
|
|
);
|
|
/* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
|
|
SMC_PMPROT = 0x00U; /* Setup Power mode protection register */
|
|
|
|
//Interrupt priority base setting
|
|
Cpu_SetBASEPRI(0);
|
|
}
|
|
|
|
|
|
|
|
|
|
/* END Cpu. */
|
|
|
|
#ifdef __cplusplus
|
|
} /* extern "C" */
|
|
#endif
|
|
|
|
/*!
|
|
** @}
|
|
*/
|
|
/*
|
|
** ###################################################################
|
|
**
|
|
** This file was created by Processor Expert 10.4 [05.11]
|
|
** for the Freescale Kinetis series of microcontrollers.
|
|
**
|
|
** ###################################################################
|
|
*/
|